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authorDavid S. Miller <davem@davemloft.net>2008-09-10 06:52:51 -0400
committerDavid S. Miller <davem@davemloft.net>2008-09-11 02:11:58 -0400
commite6e003720fd7123482f77dcec19e930d272937fe (patch)
tree4b08ce49ffc264b7c2e8ae9a7c4650e9f4eff63b /arch/sparc64/kernel
parent1c03a55cdf309d0939e881b313abbe7e9a67d95e (diff)
sparc64: Commonize large portions of PSYCHO error handling.
The IOMMU and streaming cache error interrogation is moved here as well as the PCI error interrupt handler. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel')
-rw-r--r--arch/sparc64/kernel/pci_psycho.c361
-rw-r--r--arch/sparc64/kernel/pci_sabre.c223
-rw-r--r--arch/sparc64/kernel/psycho_common.c353
-rw-r--r--arch/sparc64/kernel/psycho_common.h11
4 files changed, 369 insertions, 579 deletions
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index 2de51fb34ee7..bac9c1ba40e0 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -98,9 +98,6 @@ static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
98} 98}
99 99
100/* PSYCHO error handling support. */ 100/* PSYCHO error handling support. */
101enum psycho_error_type {
102 UE_ERR, CE_ERR, PCI_ERR
103};
104 101
105/* Helper function of IOMMU error checking, which checks out 102/* Helper function of IOMMU error checking, which checks out
106 * the state of the streaming buffers. The IOMMU lock is 103 * the state of the streaming buffers. The IOMMU lock is
@@ -125,112 +122,10 @@ enum psycho_error_type {
125#define PSYCHO_STC_DATA_B 0xc000UL 122#define PSYCHO_STC_DATA_B 0xc000UL
126#define PSYCHO_STC_ERR_A 0xb400UL 123#define PSYCHO_STC_ERR_A 0xb400UL
127#define PSYCHO_STC_ERR_B 0xc400UL 124#define PSYCHO_STC_ERR_B 0xc400UL
128#define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
129#define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
130#define PSYCHO_STC_TAG_A 0xb800UL 125#define PSYCHO_STC_TAG_A 0xb800UL
131#define PSYCHO_STC_TAG_B 0xc800UL 126#define PSYCHO_STC_TAG_B 0xc800UL
132#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
133#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
134#define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
135#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
136#define PSYCHO_STC_LINE_A 0xb900UL 127#define PSYCHO_STC_LINE_A 0xb900UL
137#define PSYCHO_STC_LINE_B 0xc900UL 128#define PSYCHO_STC_LINE_B 0xc900UL
138#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
139#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
140#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
141#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
142#define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
143#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
144
145static DEFINE_SPINLOCK(stc_buf_lock);
146static unsigned long stc_error_buf[128];
147static unsigned long stc_tag_buf[16];
148static unsigned long stc_line_buf[16];
149
150static void psycho_check_stc_error(struct pci_pbm_info *pbm)
151{
152 struct strbuf *strbuf = &pbm->stc;
153 unsigned long err_base, tag_base, line_base;
154 u64 control;
155 int i;
156
157 err_base = strbuf->strbuf_err_stat;
158 tag_base = strbuf->strbuf_tag_diag;
159 line_base = strbuf->strbuf_line_diag;
160
161 spin_lock(&stc_buf_lock);
162
163 /* This is __REALLY__ dangerous. When we put the
164 * streaming buffer into diagnostic mode to probe
165 * it's tags and error status, we _must_ clear all
166 * of the line tag valid bits before re-enabling
167 * the streaming buffer. If any dirty data lives
168 * in the STC when we do this, we will end up
169 * invalidating it before it has a chance to reach
170 * main memory.
171 */
172 control = psycho_read(strbuf->strbuf_control);
173 psycho_write(strbuf->strbuf_control,
174 (control | PSYCHO_STRBUF_CTRL_DENAB));
175 for (i = 0; i < 128; i++) {
176 unsigned long val;
177
178 val = psycho_read(err_base + (i * 8UL));
179 psycho_write(err_base + (i * 8UL), 0UL);
180 stc_error_buf[i] = val;
181 }
182 for (i = 0; i < 16; i++) {
183 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
184 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
185 psycho_write(tag_base + (i * 8UL), 0UL);
186 psycho_write(line_base + (i * 8UL), 0UL);
187 }
188
189 /* OK, state is logged, exit diagnostic mode. */
190 psycho_write(strbuf->strbuf_control, control);
191
192 for (i = 0; i < 16; i++) {
193 int j, saw_error, first, last;
194
195 saw_error = 0;
196 first = i * 8;
197 last = first + 8;
198 for (j = first; j < last; j++) {
199 unsigned long errval = stc_error_buf[j];
200 if (errval != 0) {
201 saw_error++;
202 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
203 pbm->name,
204 j,
205 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
206 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
207 }
208 }
209 if (saw_error != 0) {
210 unsigned long tagval = stc_tag_buf[i];
211 unsigned long lineval = stc_line_buf[i];
212 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
213 pbm->name,
214 i,
215 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
216 (tagval & PSYCHO_STCTAG_VPN),
217 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
218 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
219 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
220 "V(%d)FOFN(%d)]\n",
221 pbm->name,
222 i,
223 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
224 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
225 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
226 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
227 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
228 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
229 }
230 }
231
232 spin_unlock(&stc_buf_lock);
233}
234 129
235/* When an Uncorrectable Error or a PCI Error happens, we 130/* When an Uncorrectable Error or a PCI Error happens, we
236 * interrogate the IOMMU state to see if it is the cause. 131 * interrogate the IOMMU state to see if it is the cause.
@@ -257,122 +152,7 @@ static void psycho_check_stc_error(struct pci_pbm_info *pbm)
257#define PSYCHO_IOMMU_TSBBASE 0x0208UL 152#define PSYCHO_IOMMU_TSBBASE 0x0208UL
258#define PSYCHO_IOMMU_FLUSH 0x0210UL 153#define PSYCHO_IOMMU_FLUSH 0x0210UL
259#define PSYCHO_IOMMU_TAG 0xa580UL 154#define PSYCHO_IOMMU_TAG 0xa580UL
260#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
261#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
262#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
263#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
264#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
265#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
266#define PSYCHO_IOMMU_DATA 0xa600UL 155#define PSYCHO_IOMMU_DATA 0xa600UL
267#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
268#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
269#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
270static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
271 unsigned long afsr,
272 unsigned long afar,
273 enum psycho_error_type type)
274{
275 struct iommu *iommu = pbm->iommu;
276 unsigned long iommu_tag[16];
277 unsigned long iommu_data[16];
278 unsigned long flags;
279 u64 control;
280 int i;
281
282 spin_lock_irqsave(&iommu->lock, flags);
283 control = psycho_read(iommu->iommu_control);
284 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
285 char *type_string;
286
287 /* Clear the error encountered bit. */
288 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
289 psycho_write(iommu->iommu_control, control);
290
291 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
292 case 0:
293 type_string = "Protection Error";
294 break;
295 case 1:
296 type_string = "Invalid Error";
297 break;
298 case 2:
299 type_string = "TimeOut Error";
300 break;
301 case 3:
302 default:
303 type_string = "ECC Error";
304 break;
305 };
306 printk("%s: IOMMU Error, type[%s]\n",
307 pbm->name, type_string);
308
309 /* Put the IOMMU into diagnostic mode and probe
310 * it's TLB for entries with error status.
311 *
312 * It is very possible for another DVMA to occur
313 * while we do this probe, and corrupt the system
314 * further. But we are so screwed at this point
315 * that we are likely to crash hard anyways, so
316 * get as much diagnostic information to the
317 * console as we can.
318 */
319 psycho_write(iommu->iommu_control,
320 control | PSYCHO_IOMMU_CTRL_DENAB);
321 for (i = 0; i < 16; i++) {
322 unsigned long base = pbm->controller_regs;
323
324 iommu_tag[i] =
325 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
326 iommu_data[i] =
327 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
328
329 /* Now clear out the entry. */
330 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
331 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
332 }
333
334 /* Leave diagnostic mode. */
335 psycho_write(iommu->iommu_control, control);
336
337 for (i = 0; i < 16; i++) {
338 unsigned long tag, data;
339
340 tag = iommu_tag[i];
341 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
342 continue;
343
344 data = iommu_data[i];
345 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
346 case 0:
347 type_string = "Protection Error";
348 break;
349 case 1:
350 type_string = "Invalid Error";
351 break;
352 case 2:
353 type_string = "TimeOut Error";
354 break;
355 case 3:
356 default:
357 type_string = "ECC Error";
358 break;
359 };
360 printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
361 pbm->name, i, type_string,
362 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
363 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
364 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
365 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
366 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
367 pbm->name, i,
368 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
369 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
370 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
371 }
372 }
373 psycho_check_stc_error(pbm);
374 spin_unlock_irqrestore(&iommu->lock, flags);
375}
376 156
377/* Uncorrectable Errors. Cause of the error and the address are 157/* Uncorrectable Errors. Cause of the error and the address are
378 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors 158 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
@@ -540,150 +320,9 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
540 */ 320 */
541#define PSYCHO_PCI_AFSR_A 0x2010UL 321#define PSYCHO_PCI_AFSR_A 0x2010UL
542#define PSYCHO_PCI_AFSR_B 0x4010UL 322#define PSYCHO_PCI_AFSR_B 0x4010UL
543#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
544#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
545#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
546#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
547#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
548#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
549#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
550#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
551#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
552#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
553#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
554#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
555#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
556#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
557#define PSYCHO_PCI_AFAR_A 0x2018UL 323#define PSYCHO_PCI_AFAR_A 0x2018UL
558#define PSYCHO_PCI_AFAR_B 0x4018UL 324#define PSYCHO_PCI_AFAR_B 0x4018UL
559 325
560static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
561{
562 unsigned long csr, csr_error_bits;
563 irqreturn_t ret = IRQ_NONE;
564 u16 stat;
565
566 csr = psycho_read(pbm->pci_csr);
567 csr_error_bits =
568 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
569 if (csr_error_bits) {
570 /* Clear the errors. */
571 psycho_write(pbm->pci_csr, csr);
572
573 /* Log 'em. */
574 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
575 printk("%s: PCI streaming byte hole error asserted.\n",
576 pbm->name);
577 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
578 printk("%s: PCI SERR signal asserted.\n", pbm->name);
579 ret = IRQ_HANDLED;
580 }
581 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
582 if (stat & (PCI_STATUS_PARITY |
583 PCI_STATUS_SIG_TARGET_ABORT |
584 PCI_STATUS_REC_TARGET_ABORT |
585 PCI_STATUS_REC_MASTER_ABORT |
586 PCI_STATUS_SIG_SYSTEM_ERROR)) {
587 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
588 pbm->name, stat);
589 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
590 ret = IRQ_HANDLED;
591 }
592 return ret;
593}
594
595static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
596{
597 struct pci_pbm_info *pbm = dev_id;
598 unsigned long afsr_reg, afar_reg;
599 unsigned long afsr, afar, error_bits;
600 int reported;
601
602 afsr_reg = pbm->pci_afsr;
603 afar_reg = pbm->pci_afar;
604
605 /* Latch error status. */
606 afar = psycho_read(afar_reg);
607 afsr = psycho_read(afsr_reg);
608
609 /* Clear primary/secondary error status bits. */
610 error_bits = afsr &
611 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
612 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
613 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
614 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
615 if (!error_bits)
616 return psycho_pcierr_intr_other(pbm);
617 psycho_write(afsr_reg, error_bits);
618
619 /* Log the error. */
620 printk("%s: PCI Error, primary error type[%s]\n",
621 pbm->name,
622 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
623 "Master Abort" :
624 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
625 "Target Abort" :
626 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
627 "Excessive Retries" :
628 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
629 "Parity Error" : "???"))))));
630 printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
631 pbm->name,
632 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
633 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
634 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
635 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
636 printk("%s: PCI Secondary errors [", pbm->name);
637 reported = 0;
638 if (afsr & PSYCHO_PCIAFSR_SMA) {
639 reported++;
640 printk("(Master Abort)");
641 }
642 if (afsr & PSYCHO_PCIAFSR_STA) {
643 reported++;
644 printk("(Target Abort)");
645 }
646 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
647 reported++;
648 printk("(Excessive Retries)");
649 }
650 if (afsr & PSYCHO_PCIAFSR_SPERR) {
651 reported++;
652 printk("(Parity Error)");
653 }
654 if (!reported)
655 printk("(none)");
656 printk("]\n");
657
658 /* For the error types shown, scan PBM's PCI bus for devices
659 * which have logged that error type.
660 */
661
662 /* If we see a Target Abort, this could be the result of an
663 * IOMMU translation error of some sort. It is extremely
664 * useful to log this information as usually it indicates
665 * a bug in the IOMMU support code or a PCI device driver.
666 */
667 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
668 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
669 pci_scan_for_target_abort(pbm, pbm->pci_bus);
670 }
671 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
672 pci_scan_for_master_abort(pbm, pbm->pci_bus);
673
674 /* For excessive retries, PSYCHO/PBM will abort the device
675 * and there is no way to specifically check for excessive
676 * retries in the config space status registers. So what
677 * we hope is that we'll catch it via the master/target
678 * abort events.
679 */
680
681 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
682 pci_scan_for_parity_error(pbm, pbm->pci_bus);
683
684 return IRQ_HANDLED;
685}
686
687/* XXX What about PowerFail/PowerManagement??? -DaveM */ 326/* XXX What about PowerFail/PowerManagement??? -DaveM */
688#define PSYCHO_ECC_CTRL 0x0020 327#define PSYCHO_ECC_CTRL 0x0020
689#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 328#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index ae11d67388e1..f8089aa84f64 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -210,95 +210,6 @@
210static int hummingbird_p; 210static int hummingbird_p;
211static struct pci_bus *sabre_root_bus; 211static struct pci_bus *sabre_root_bus;
212 212
213/* SABRE error handling support. */
214static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
215 unsigned long afsr,
216 unsigned long afar)
217{
218 struct iommu *iommu = pbm->iommu;
219 unsigned long iommu_tag[16];
220 unsigned long iommu_data[16];
221 unsigned long flags;
222 u64 control;
223 int i;
224
225 spin_lock_irqsave(&iommu->lock, flags);
226 control = sabre_read(iommu->iommu_control);
227 if (control & SABRE_IOMMUCTRL_ERR) {
228 char *type_string;
229
230 /* Clear the error encountered bit.
231 * NOTE: On Sabre this is write 1 to clear,
232 * which is different from Psycho.
233 */
234 sabre_write(iommu->iommu_control, control);
235 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
236 case 1:
237 type_string = "Invalid Error";
238 break;
239 case 3:
240 type_string = "ECC Error";
241 break;
242 default:
243 type_string = "Unknown";
244 break;
245 };
246 printk("%s: IOMMU Error, type[%s]\n",
247 pbm->name, type_string);
248
249 /* Enter diagnostic mode and probe for error'd
250 * entries in the IOTLB.
251 */
252 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
253 sabre_write(iommu->iommu_control,
254 (control | SABRE_IOMMUCTRL_DENAB));
255 for (i = 0; i < 16; i++) {
256 unsigned long base = pbm->controller_regs;
257
258 iommu_tag[i] =
259 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
260 iommu_data[i] =
261 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
262 sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
263 sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
264 }
265 sabre_write(iommu->iommu_control, control);
266
267 for (i = 0; i < 16; i++) {
268 unsigned long tag, data;
269
270 tag = iommu_tag[i];
271 if (!(tag & SABRE_IOMMUTAG_ERR))
272 continue;
273
274 data = iommu_data[i];
275 switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
276 case 1:
277 type_string = "Invalid Error";
278 break;
279 case 3:
280 type_string = "ECC Error";
281 break;
282 default:
283 type_string = "Unknown";
284 break;
285 };
286 printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
287 pbm->name, i, tag, type_string,
288 ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
289 ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
290 ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
291 printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
292 pbm->name, i, data,
293 ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
294 ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
295 ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
296 ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
297 }
298 }
299 spin_unlock_irqrestore(&iommu->lock, flags);
300}
301
302static irqreturn_t sabre_ue_intr(int irq, void *dev_id) 213static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
303{ 214{
304 struct pci_pbm_info *pbm = dev_id; 215 struct pci_pbm_info *pbm = dev_id;
@@ -354,7 +265,7 @@ static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
354 printk("]\n"); 265 printk("]\n");
355 266
356 /* Interrogate IOMMU for error status. */ 267 /* Interrogate IOMMU for error status. */
357 sabre_check_iommu_error(pbm, afsr, afar); 268 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
358 269
359 return IRQ_HANDLED; 270 return IRQ_HANDLED;
360} 271}
@@ -415,133 +326,6 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
415 return IRQ_HANDLED; 326 return IRQ_HANDLED;
416} 327}
417 328
418static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm)
419{
420 unsigned long csr_reg, csr, csr_error_bits;
421 irqreturn_t ret = IRQ_NONE;
422 u16 stat;
423
424 csr_reg = pbm->controller_regs + SABRE_PCICTRL;
425 csr = sabre_read(csr_reg);
426 csr_error_bits =
427 csr & SABRE_PCICTRL_SERR;
428 if (csr_error_bits) {
429 /* Clear the errors. */
430 sabre_write(csr_reg, csr);
431
432 /* Log 'em. */
433 if (csr_error_bits & SABRE_PCICTRL_SERR)
434 printk("%s: PCI SERR signal asserted.\n",
435 pbm->name);
436 ret = IRQ_HANDLED;
437 }
438 pci_bus_read_config_word(sabre_root_bus, 0,
439 PCI_STATUS, &stat);
440 if (stat & (PCI_STATUS_PARITY |
441 PCI_STATUS_SIG_TARGET_ABORT |
442 PCI_STATUS_REC_TARGET_ABORT |
443 PCI_STATUS_REC_MASTER_ABORT |
444 PCI_STATUS_SIG_SYSTEM_ERROR)) {
445 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
446 pbm->name, stat);
447 pci_bus_write_config_word(sabre_root_bus, 0,
448 PCI_STATUS, 0xffff);
449 ret = IRQ_HANDLED;
450 }
451 return ret;
452}
453
454static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
455{
456 struct pci_pbm_info *pbm = dev_id;
457 unsigned long afsr_reg, afar_reg;
458 unsigned long afsr, afar, error_bits;
459 int reported;
460
461 afsr_reg = pbm->controller_regs + SABRE_PIOAFSR;
462 afar_reg = pbm->controller_regs + SABRE_PIOAFAR;
463
464 /* Latch error status. */
465 afar = sabre_read(afar_reg);
466 afsr = sabre_read(afsr_reg);
467
468 /* Clear primary/secondary error status bits. */
469 error_bits = afsr &
470 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
471 SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
472 SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
473 SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
474 if (!error_bits)
475 return sabre_pcierr_intr_other(pbm);
476 sabre_write(afsr_reg, error_bits);
477
478 /* Log the error. */
479 printk("%s: PCI Error, primary error type[%s]\n",
480 pbm->name,
481 (((error_bits & SABRE_PIOAFSR_PMA) ?
482 "Master Abort" :
483 ((error_bits & SABRE_PIOAFSR_PTA) ?
484 "Target Abort" :
485 ((error_bits & SABRE_PIOAFSR_PRTRY) ?
486 "Excessive Retries" :
487 ((error_bits & SABRE_PIOAFSR_PPERR) ?
488 "Parity Error" : "???"))))));
489 printk("%s: bytemask[%04lx] was_block(%d)\n",
490 pbm->name,
491 (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
492 (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
493 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
494 printk("%s: PCI Secondary errors [", pbm->name);
495 reported = 0;
496 if (afsr & SABRE_PIOAFSR_SMA) {
497 reported++;
498 printk("(Master Abort)");
499 }
500 if (afsr & SABRE_PIOAFSR_STA) {
501 reported++;
502 printk("(Target Abort)");
503 }
504 if (afsr & SABRE_PIOAFSR_SRTRY) {
505 reported++;
506 printk("(Excessive Retries)");
507 }
508 if (afsr & SABRE_PIOAFSR_SPERR) {
509 reported++;
510 printk("(Parity Error)");
511 }
512 if (!reported)
513 printk("(none)");
514 printk("]\n");
515
516 /* For the error types shown, scan both PCI buses for devices
517 * which have logged that error type.
518 */
519
520 /* If we see a Target Abort, this could be the result of an
521 * IOMMU translation error of some sort. It is extremely
522 * useful to log this information as usually it indicates
523 * a bug in the IOMMU support code or a PCI device driver.
524 */
525 if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
526 sabre_check_iommu_error(pbm, afsr, afar);
527 pci_scan_for_target_abort(pbm, pbm->pci_bus);
528 }
529 if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
530 pci_scan_for_master_abort(pbm, pbm->pci_bus);
531
532 /* For excessive retries, SABRE/PBM will abort the device
533 * and there is no way to specifically check for excessive
534 * retries in the config space status registers. So what
535 * we hope is that we'll catch it via the master/target
536 * abort events.
537 */
538
539 if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
540 pci_scan_for_parity_error(pbm, pbm->pci_bus);
541
542 return IRQ_HANDLED;
543}
544
545static void sabre_register_error_handlers(struct pci_pbm_info *pbm) 329static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
546{ 330{
547 struct device_node *dp = pbm->op->node; 331 struct device_node *dp = pbm->op->node;
@@ -588,7 +372,7 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
588 if (err) 372 if (err)
589 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n", 373 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
590 pbm->name, err); 374 pbm->name, err);
591 err = request_irq(op->irqs[0], sabre_pcierr_intr, 0, 375 err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
592 "SABRE_PCIERR", pbm); 376 "SABRE_PCIERR", pbm);
593 if (err) 377 if (err)
594 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n", 378 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
@@ -679,6 +463,9 @@ static void __init sabre_pbm_init(struct pci_pbm_info *pbm,
679 struct of_device *op) 463 struct of_device *op)
680{ 464{
681 psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE); 465 psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);
466 pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;
467 pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;
468 pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;
682 sabre_scan_bus(pbm, &op->dev); 469 sabre_scan_bus(pbm, &op->dev);
683} 470}
684 471
diff --git a/arch/sparc64/kernel/psycho_common.c b/arch/sparc64/kernel/psycho_common.c
index 1b4d462513df..6b188dfeeb9d 100644
--- a/arch/sparc64/kernel/psycho_common.c
+++ b/arch/sparc64/kernel/psycho_common.c
@@ -3,15 +3,368 @@
3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net> 3 * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
4 */ 4 */
5#include <linux/kernel.h> 5#include <linux/kernel.h>
6#include <linux/interrupt.h>
6 7
7#include <asm/upa.h> 8#include <asm/upa.h>
8 9
9#include "pci_impl.h" 10#include "pci_impl.h"
11#include "iommu_common.h"
10#include "psycho_common.h" 12#include "psycho_common.h"
11 13
14#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL
15#define PSYCHO_STCERR_WRITE 0x0000000000000002UL
16#define PSYCHO_STCERR_READ 0x0000000000000001UL
17#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL
18#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL
19#define PSYCHO_STCTAG_VALID 0x0000000000000002UL
20#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL
21#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL
22#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL
23#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL
24#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL
25#define PSYCHO_STCLINE_VALID 0x0000000000000002UL
26#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL
27
28static DEFINE_SPINLOCK(stc_buf_lock);
29static unsigned long stc_error_buf[128];
30static unsigned long stc_tag_buf[16];
31static unsigned long stc_line_buf[16];
32
33static void psycho_check_stc_error(struct pci_pbm_info *pbm)
34{
35 unsigned long err_base, tag_base, line_base;
36 struct strbuf *strbuf = &pbm->stc;
37 u64 control;
38 int i;
39
40 if (!strbuf->strbuf_control)
41 return;
42
43 err_base = strbuf->strbuf_err_stat;
44 tag_base = strbuf->strbuf_tag_diag;
45 line_base = strbuf->strbuf_line_diag;
46
47 spin_lock(&stc_buf_lock);
48
49 /* This is __REALLY__ dangerous. When we put the streaming
50 * buffer into diagnostic mode to probe it's tags and error
51 * status, we _must_ clear all of the line tag valid bits
52 * before re-enabling the streaming buffer. If any dirty data
53 * lives in the STC when we do this, we will end up
54 * invalidating it before it has a chance to reach main
55 * memory.
56 */
57 control = upa_readq(strbuf->strbuf_control);
58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control);
59 for (i = 0; i < 128; i++) {
60 u64 val;
61
62 val = upa_readq(err_base + (i * 8UL));
63 upa_writeq(0UL, err_base + (i * 8UL));
64 stc_error_buf[i] = val;
65 }
66 for (i = 0; i < 16; i++) {
67 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
68 stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
69 upa_writeq(0UL, tag_base + (i * 8UL));
70 upa_writeq(0UL, line_base + (i * 8UL));
71 }
72
73 /* OK, state is logged, exit diagnostic mode. */
74 upa_writeq(control, strbuf->strbuf_control);
75
76 for (i = 0; i < 16; i++) {
77 int j, saw_error, first, last;
78
79 saw_error = 0;
80 first = i * 8;
81 last = first + 8;
82 for (j = first; j < last; j++) {
83 u64 errval = stc_error_buf[j];
84 if (errval != 0) {
85 saw_error++;
86 printk(KERN_ERR "%s: STC_ERR(%d)[wr(%d)"
87 "rd(%d)]\n",
88 pbm->name,
89 j,
90 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
91 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
92 }
93 }
94 if (saw_error != 0) {
95 u64 tagval = stc_tag_buf[i];
96 u64 lineval = stc_line_buf[i];
97 printk(KERN_ERR "%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)"
98 "V(%d)W(%d)]\n",
99 pbm->name,
100 i,
101 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
102 (tagval & PSYCHO_STCTAG_VPN),
103 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
104 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
105 printk(KERN_ERR "%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)"
106 "LADDR(%lx)EP(%lx)V(%d)FOFN(%d)]\n",
107 pbm->name,
108 i,
109 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
110 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
111 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
112 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
113 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
114 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
115 }
116 }
117
118 spin_unlock(&stc_buf_lock);
119}
120
12#define PSYCHO_IOMMU_TAG 0xa580UL 121#define PSYCHO_IOMMU_TAG 0xa580UL
13#define PSYCHO_IOMMU_DATA 0xa600UL 122#define PSYCHO_IOMMU_DATA 0xa600UL
14 123
124static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm,
125 u64 *tag, u64 *data)
126{
127 int i;
128
129 for (i = 0; i < 16; i++) {
130 unsigned long base = pbm->controller_regs;
131 unsigned long off = i * 8UL;
132
133 tag[i] = upa_readq(base + PSYCHO_IOMMU_TAG+off);
134 data[i] = upa_readq(base + PSYCHO_IOMMU_DATA+off);
135
136 /* Now clear out the entry. */
137 upa_writeq(0, base + PSYCHO_IOMMU_TAG + off);
138 upa_writeq(0, base + PSYCHO_IOMMU_DATA + off);
139 }
140}
141
142#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
143#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
144#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
145#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
146#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
147#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
148#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
149#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
150#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
151
152static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm,
153 u64 *tag, u64 *data)
154{
155 int i;
156
157 for (i = 0; i < 16; i++) {
158 u64 tag_val, data_val;
159 const char *type_str;
160 tag_val = tag[i];
161 if (!(tag_val & PSYCHO_IOMMU_TAG_ERR))
162 continue;
163
164 data_val = data[i];
165 switch((tag_val & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
166 case 0:
167 type_str = "Protection Error";
168 break;
169 case 1:
170 type_str = "Invalid Error";
171 break;
172 case 2:
173 type_str = "TimeOut Error";
174 break;
175 case 3:
176 default:
177 type_str = "ECC Error";
178 break;
179 }
180
181 printk(KERN_ERR "%s: IOMMU TAG(%d)[error(%s) wr(%d) "
182 "str(%d) sz(%dK) vpg(%08lx)]\n",
183 pbm->name, i, type_str,
184 ((tag_val & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
185 ((tag_val & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
186 ((tag_val & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
187 (tag_val & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
188 printk(KERN_ERR "%s: IOMMU DATA(%d)[valid(%d) cache(%d) "
189 "ppg(%016lx)]\n",
190 pbm->name, i,
191 ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
192 ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
193 (data_val & PSYCHO_IOMMU_DATA_PPAGE)<<IOMMU_PAGE_SHIFT);
194 }
195}
196
197#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL
198#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL
199
200void psycho_check_iommu_error(struct pci_pbm_info *pbm,
201 unsigned long afsr,
202 unsigned long afar,
203 enum psycho_error_type type)
204{
205 u64 control, iommu_tag[16], iommu_data[16];
206 struct iommu *iommu = pbm->iommu;
207 unsigned long flags;
208
209 spin_lock_irqsave(&iommu->lock, flags);
210 control = upa_readq(iommu->iommu_control);
211 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
212 const char *type_str;
213
214 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
215 upa_writeq(control, iommu->iommu_control);
216
217 switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
218 case 0:
219 type_str = "Protection Error";
220 break;
221 case 1:
222 type_str = "Invalid Error";
223 break;
224 case 2:
225 type_str = "TimeOut Error";
226 break;
227 case 3:
228 default:
229 type_str = "ECC Error";
230 break;
231 };
232 printk(KERN_ERR "%s: IOMMU Error, type[%s]\n",
233 pbm->name, type_str);
234
235 /* It is very possible for another DVMA to occur while
236 * we do this probe, and corrupt the system further.
237 * But we are so screwed at this point that we are
238 * likely to crash hard anyways, so get as much
239 * diagnostic information to the console as we can.
240 */
241 psycho_record_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
242 psycho_dump_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
243 }
244 psycho_check_stc_error(pbm);
245 spin_unlock_irqrestore(&iommu->lock, flags);
246}
247
248#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL
249#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL
250
251static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
252{
253 irqreturn_t ret = IRQ_NONE;
254 u64 csr, csr_error_bits;
255 u16 stat;
256
257 csr = upa_readq(pbm->pci_csr);
258 csr_error_bits = csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
259 if (csr_error_bits) {
260 /* Clear the errors. */
261 upa_writeq(csr, pbm->pci_csr);
262
263 /* Log 'em. */
264 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
265 printk(KERN_ERR "%s: PCI streaming byte hole "
266 "error asserted.\n", pbm->name);
267 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
268 printk(KERN_ERR "%s: PCI SERR signal asserted.\n",
269 pbm->name);
270 ret = IRQ_HANDLED;
271 }
272 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
273 if (stat & (PCI_STATUS_PARITY |
274 PCI_STATUS_SIG_TARGET_ABORT |
275 PCI_STATUS_REC_TARGET_ABORT |
276 PCI_STATUS_REC_MASTER_ABORT |
277 PCI_STATUS_SIG_SYSTEM_ERROR)) {
278 printk(KERN_ERR "%s: PCI bus error, PCI_STATUS[%04x]\n",
279 pbm->name, stat);
280 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
281 ret = IRQ_HANDLED;
282 }
283 return ret;
284}
285
286#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL
287#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL
288#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL
289#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL
290#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL
291#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL
292#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL
293#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL
294#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL
295#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL
296#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL
297#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL
298#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL
299#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL
300
301irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
302{
303 struct pci_pbm_info *pbm = dev_id;
304 u64 afsr, afar, error_bits;
305 int reported;
306
307 afsr = upa_readq(pbm->pci_afsr);
308 afar = upa_readq(pbm->pci_afar);
309 error_bits = afsr &
310 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
311 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
312 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
313 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
314 if (!error_bits)
315 return psycho_pcierr_intr_other(pbm);
316 upa_writeq(error_bits, pbm->pci_afsr);
317 printk(KERN_ERR "%s: PCI Error, primary error type[%s]\n",
318 pbm->name,
319 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
320 "Master Abort" :
321 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
322 "Target Abort" :
323 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
324 "Excessive Retries" :
325 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
326 "Parity Error" : "???"))))));
327 printk(KERN_ERR "%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
328 pbm->name,
329 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
330 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
331 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
332 printk(KERN_ERR "%s: PCI AFAR [%016lx]\n", pbm->name, afar);
333 printk(KERN_ERR "%s: PCI Secondary errors [", pbm->name);
334 reported = 0;
335 if (afsr & PSYCHO_PCIAFSR_SMA) {
336 reported++;
337 printk("(Master Abort)");
338 }
339 if (afsr & PSYCHO_PCIAFSR_STA) {
340 reported++;
341 printk("(Target Abort)");
342 }
343 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
344 reported++;
345 printk("(Excessive Retries)");
346 }
347 if (afsr & PSYCHO_PCIAFSR_SPERR) {
348 reported++;
349 printk("(Parity Error)");
350 }
351 if (!reported)
352 printk("(none)");
353 printk("]\n");
354
355 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
356 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
357 pci_scan_for_target_abort(pbm, pbm->pci_bus);
358 }
359 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
360 pci_scan_for_master_abort(pbm, pbm->pci_bus);
361
362 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
363 pci_scan_for_parity_error(pbm, pbm->pci_bus);
364
365 return IRQ_HANDLED;
366}
367
15static void psycho_iommu_flush(struct pci_pbm_info *pbm) 368static void psycho_iommu_flush(struct pci_pbm_info *pbm)
16{ 369{
17 int i; 370 int i;
diff --git a/arch/sparc64/kernel/psycho_common.h b/arch/sparc64/kernel/psycho_common.h
index adfbadb6986e..b53aa8dcad2c 100644
--- a/arch/sparc64/kernel/psycho_common.h
+++ b/arch/sparc64/kernel/psycho_common.h
@@ -1,6 +1,17 @@
1#ifndef _PSYCHO_COMMON_H 1#ifndef _PSYCHO_COMMON_H
2#define _PSYCHO_COMMON_H 2#define _PSYCHO_COMMON_H
3 3
4enum psycho_error_type {
5 UE_ERR, CE_ERR, PCI_ERR
6};
7
8extern void psycho_check_iommu_error(struct pci_pbm_info *pbm,
9 unsigned long afsr,
10 unsigned long afar,
11 enum psycho_error_type type);
12
13extern irqreturn_t psycho_pcierr_intr(int irq, void *dev_id);
14
4extern int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize, 15extern int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize,
5 u32 dvma_offset, u32 dma_mask, 16 u32 dvma_offset, u32 dma_mask,
6 unsigned long write_complete_offset); 17 unsigned long write_complete_offset);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 10:48:47 -0500