diff options
author | David S. Miller <davem@sunset.davemloft.net> | 2006-02-09 23:20:34 -0500 |
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committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 04:12:07 -0500 |
commit | ed6b0b45437dcf7ef1c48b3be413bebcc84771d8 (patch) | |
tree | e52dbcebe1435f9d2957b55c100824cb7b8b1f98 /arch/sparc64/kernel/winfixup.S | |
parent | 618e9ed98aed924a1fc664eb6522db4a5e927043 (diff) |
[SPARC64]: SUN4V memory exception trap handlers.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/winfixup.S')
-rw-r--r-- | arch/sparc64/kernel/winfixup.S | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/arch/sparc64/kernel/winfixup.S b/arch/sparc64/kernel/winfixup.S index efe2770e8f5d..aca2a98b930b 100644 --- a/arch/sparc64/kernel/winfixup.S +++ b/arch/sparc64/kernel/winfixup.S | |||
@@ -109,16 +109,23 @@ winfix_mna: | |||
109 | done | 109 | done |
110 | 110 | ||
111 | fill_fixup_mna: | 111 | fill_fixup_mna: |
112 | TRAP_LOAD_THREAD_REG(%g6, %g1) | ||
113 | rdpr %tstate, %g1 | 112 | rdpr %tstate, %g1 |
114 | and %g1, TSTATE_CWP, %g1 | 113 | and %g1, TSTATE_CWP, %g1 |
115 | wrpr %g1, %cwp | 114 | wrpr %g1, %cwp |
116 | ba,pt %xcc, etrap | 115 | ba,pt %xcc, etrap |
117 | rd %pc, %g7 | 116 | rd %pc, %g7 |
118 | mov %l4, %o2 | 117 | sethi %hi(tlb_type), %g1 |
119 | mov %l5, %o1 | 118 | mov %l4, %o1 |
120 | call mem_address_unaligned | 119 | lduw [%g1 + %lo(tlb_type)], %g1 |
120 | mov %l5, %o2 | ||
121 | cmp %g1, 3 | ||
122 | bne,pt %icc, 1f | ||
121 | add %sp, PTREGS_OFF, %o0 | 123 | add %sp, PTREGS_OFF, %o0 |
124 | call sun4v_mna | ||
125 | nop | ||
126 | ba,a,pt %xcc, rtrap_clr_l6 | ||
127 | 1: call mem_address_unaligned | ||
128 | nop | ||
122 | ba,a,pt %xcc, rtrap_clr_l6 | 129 | ba,a,pt %xcc, rtrap_clr_l6 |
123 | 130 | ||
124 | winfix_dax: | 131 | winfix_dax: |
@@ -128,14 +135,21 @@ winfix_dax: | |||
128 | done | 135 | done |
129 | 136 | ||
130 | fill_fixup_dax: | 137 | fill_fixup_dax: |
131 | TRAP_LOAD_THREAD_REG(%g6, %g1) | ||
132 | rdpr %tstate, %g1 | 138 | rdpr %tstate, %g1 |
133 | and %g1, TSTATE_CWP, %g1 | 139 | and %g1, TSTATE_CWP, %g1 |
134 | wrpr %g1, %cwp | 140 | wrpr %g1, %cwp |
135 | ba,pt %xcc, etrap | 141 | ba,pt %xcc, etrap |
136 | rd %pc, %g7 | 142 | rd %pc, %g7 |
143 | sethi %hi(tlb_type), %g1 | ||
137 | mov %l4, %o1 | 144 | mov %l4, %o1 |
145 | lduw [%g1 + %lo(tlb_type)], %g1 | ||
138 | mov %l5, %o2 | 146 | mov %l5, %o2 |
139 | call spitfire_data_access_exception | 147 | cmp %g1, 3 |
148 | bne,pt %icc, 1f | ||
140 | add %sp, PTREGS_OFF, %o0 | 149 | add %sp, PTREGS_OFF, %o0 |
150 | call sun4v_data_access_exception | ||
151 | nop | ||
152 | ba,a,pt %xcc, rtrap_clr_l6 | ||
153 | 1: call spitfire_data_access_exception | ||
154 | nop | ||
141 | ba,a,pt %xcc, rtrap_clr_l6 | 155 | ba,a,pt %xcc, rtrap_clr_l6 |