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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-09 23:20:34 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 04:12:07 -0500
commited6b0b45437dcf7ef1c48b3be413bebcc84771d8 (patch)
treee52dbcebe1435f9d2957b55c100824cb7b8b1f98 /arch/sparc64/kernel/sun4v_tlb_miss.S
parent618e9ed98aed924a1fc664eb6522db4a5e927043 (diff)
[SPARC64]: SUN4V memory exception trap handlers.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/sun4v_tlb_miss.S')
-rw-r--r--arch/sparc64/kernel/sun4v_tlb_miss.S170
1 files changed, 170 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/sun4v_tlb_miss.S b/arch/sparc64/kernel/sun4v_tlb_miss.S
index b8678b5557aa..c408b05a5f0a 100644
--- a/arch/sparc64/kernel/sun4v_tlb_miss.S
+++ b/arch/sparc64/kernel/sun4v_tlb_miss.S
@@ -237,6 +237,167 @@ sun4v_tsb_miss_common:
237 ba,pt %xcc, tsb_miss_page_table_walk 237 ba,pt %xcc, tsb_miss_page_table_walk
238 add %g1, %g2, %g1 238 add %g1, %g2, %g1
239 239
240 /* Instruction Access Exception, tl0. */
241sun4v_iacc:
242 mov SCRATCHPAD_CPUID, %g1
243 ldxa [%g1] ASI_SCRATCHPAD, %g3
244 sethi %hi(trap_block), %g2
245 or %g2, %lo(trap_block), %g2
246 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
247 add %g2, %g3, %g2
248 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3
249 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
250 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
251 sllx %g3, 16, %g3
252 or %g5, %g3, %g5
253 ba,pt %xcc, etrap
254 rd %pc, %g7
255 mov %l4, %o1
256 mov %l5, %o2
257 call sun4v_insn_access_exception
258 add %sp, PTREGS_OFF, %o0
259 ba,a,pt %xcc, rtrap_clr_l6
260
261 /* Instruction Access Exception, tl1. */
262sun4v_iacc_tl1:
263 mov SCRATCHPAD_CPUID, %g1
264 ldxa [%g1] ASI_SCRATCHPAD, %g3
265 sethi %hi(trap_block), %g2
266 or %g2, %lo(trap_block), %g2
267 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
268 add %g2, %g3, %g2
269 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3
270 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
271 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
272 sllx %g3, 16, %g3
273 or %g5, %g3, %g5
274 ba,pt %xcc, etraptl1
275 rd %pc, %g7
276 mov %l4, %o1
277 mov %l5, %o2
278 call sun4v_insn_access_exception_tl1
279 add %sp, PTREGS_OFF, %o0
280 ba,a,pt %xcc, rtrap_clr_l6
281
282 /* Data Access Exception, tl0. */
283sun4v_dacc:
284 mov SCRATCHPAD_CPUID, %g1
285 ldxa [%g1] ASI_SCRATCHPAD, %g3
286 sethi %hi(trap_block), %g2
287 or %g2, %lo(trap_block), %g2
288 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
289 add %g2, %g3, %g2
290 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
291 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
292 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
293 sllx %g3, 16, %g3
294 or %g5, %g3, %g5
295 ba,pt %xcc, etrap
296 rd %pc, %g7
297 mov %l4, %o1
298 mov %l5, %o2
299 call sun4v_data_access_exception
300 add %sp, PTREGS_OFF, %o0
301 ba,a,pt %xcc, rtrap_clr_l6
302
303 /* Data Access Exception, tl1. */
304sun4v_dacc_tl1:
305 mov SCRATCHPAD_CPUID, %g1
306 ldxa [%g1] ASI_SCRATCHPAD, %g3
307 sethi %hi(trap_block), %g2
308 or %g2, %lo(trap_block), %g2
309 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
310 add %g2, %g3, %g2
311 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
312 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
313 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
314 sllx %g3, 16, %g3
315 or %g5, %g3, %g5
316 ba,pt %xcc, etraptl1
317 rd %pc, %g7
318 mov %l4, %o1
319 mov %l5, %o2
320 call sun4v_data_access_exception_tl1
321 add %sp, PTREGS_OFF, %o0
322 ba,a,pt %xcc, rtrap_clr_l6
323
324 /* Memory Address Unaligned. */
325sun4v_mna:
326 mov SCRATCHPAD_CPUID, %g1
327 ldxa [%g1] ASI_SCRATCHPAD, %g3
328 sethi %hi(trap_block), %g2
329 or %g2, %lo(trap_block), %g2
330 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
331 add %g2, %g3, %g2
332 mov HV_FAULT_TYPE_UNALIGNED, %g3
333 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
334 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
335 sllx %g3, 16, %g3
336 or %g5, %g3, %g5
337
338 /* Window fixup? */
339 rdpr %tl, %g2
340 cmp %g2, 1
341 bgu,pn %icc, winfix_mna
342 rdpr %tpc, %g3
343
344 ba,pt %xcc, etrap
345 rd %pc, %g7
346 mov %l4, %o1
347 mov %l5, %o2
348 call sun4v_mna
349 add %sp, PTREGS_OFF, %o0
350 ba,a,pt %xcc, rtrap_clr_l6
351
352 /* Privileged Action. */
353sun4v_privact:
354 ba,pt %xcc, etrap
355 rd %pc, %g7
356 call do_privact
357 add %sp, PTREGS_OFF, %o0
358 ba,a,pt %xcc, rtrap_clr_l6
359
360 /* Unaligned ldd float, tl0. */
361sun4v_lddfmna:
362 mov SCRATCHPAD_CPUID, %g1
363 ldxa [%g1] ASI_SCRATCHPAD, %g3
364 sethi %hi(trap_block), %g2
365 or %g2, %lo(trap_block), %g2
366 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
367 add %g2, %g3, %g2
368 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
369 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
370 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
371 sllx %g3, 16, %g3
372 or %g5, %g3, %g5
373 ba,pt %xcc, etrap
374 rd %pc, %g7
375 mov %l4, %o1
376 mov %l5, %o2
377 call handle_lddfmna
378 add %sp, PTREGS_OFF, %o0
379 ba,a,pt %xcc, rtrap_clr_l6
380
381 /* Unaligned std float, tl0. */
382sun4v_stdfmna:
383 mov SCRATCHPAD_CPUID, %g1
384 ldxa [%g1] ASI_SCRATCHPAD, %g3
385 sethi %hi(trap_block), %g2
386 or %g2, %lo(trap_block), %g2
387 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
388 add %g2, %g3, %g2
389 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
390 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
391 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
392 sllx %g3, 16, %g3
393 or %g5, %g3, %g5
394 ba,pt %xcc, etrap
395 rd %pc, %g7
396 mov %l4, %o1
397 mov %l5, %o2
398 call handle_stdfmna
399 add %sp, PTREGS_OFF, %o0
400 ba,a,pt %xcc, rtrap_clr_l6
240 401
241#define BRANCH_ALWAYS 0x10680000 402#define BRANCH_ALWAYS 0x10680000
242#define NOP 0x01000000 403#define NOP 0x01000000
@@ -265,6 +426,15 @@ sun4v_patch_tlb_handlers:
265 SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss) 426 SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
266 SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot) 427 SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
267 SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot) 428 SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
429 SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
430 SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
431 SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
432 SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
433 SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
434 SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
435 SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
436 SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
437 SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
268 retl 438 retl
269 nop 439 nop
270 .size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers 440 .size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers
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