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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-10 18:39:51 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 04:12:15 -0500
commit12eaa328f9fb2d3fcb5afb682c762690d05a3cd8 (patch)
treecce4e68b971757010a3e0bbf035fc65a381a3cd4 /arch/sparc64/kernel/sun4v_tlb_miss.S
parent18397944642cbca7fcd4a109b43ed5b4652e95b9 (diff)
[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.
This is where the virtual address of the fault status area belongs. To set it up we don't make a hypervisor call, instead we call OBP's SUNW,set-trap-table with the real address of the fault status area as the second argument. And right before that call we write the virtual address into ASI_SCRATCHPAD vaddr 0x0. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/sun4v_tlb_miss.S')
-rw-r--r--arch/sparc64/kernel/sun4v_tlb_miss.S162
1 files changed, 45 insertions, 117 deletions
diff --git a/arch/sparc64/kernel/sun4v_tlb_miss.S b/arch/sparc64/kernel/sun4v_tlb_miss.S
index c408b05a5f0a..f6222623de38 100644
--- a/arch/sparc64/kernel/sun4v_tlb_miss.S
+++ b/arch/sparc64/kernel/sun4v_tlb_miss.S
@@ -7,26 +7,20 @@
7 .align 32 7 .align 32
8 8
9sun4v_itlb_miss: 9sun4v_itlb_miss:
10 /* Load CPU ID into %g3. */ 10 /* Load MMU Miss base into %g2. */
11 mov SCRATCHPAD_CPUID, %g1 11 ldxa [%g0] ASI_SCRATCHPAD, %g3
12 ldxa [%g1] ASI_SCRATCHPAD, %g3
13 12
14 /* Load UTSB reg into %g1. */ 13 /* Load UTSB reg into %g1. */
15 ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1 14 mov SCRATCHPAD_UTSBREG1, %g1
16 15 ldxa [%g1] ASI_SCRATCHPAD, %g1
17 /* Load &trap_block[smp_processor_id()] into %g2. */
18 sethi %hi(trap_block), %g2
19 or %g2, %lo(trap_block), %g2
20 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
21 add %g2, %g3, %g2
22 16
23 /* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6. 17 /* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6.
24 * Branch if kernel TLB miss. The kernel TSB and user TSB miss 18 * Branch if kernel TLB miss. The kernel TSB and user TSB miss
25 * code wants the missing virtual address in %g4, so that value 19 * code wants the missing virtual address in %g4, so that value
26 * cannot be modified through the entirety of this handler. 20 * cannot be modified through the entirety of this handler.
27 */ 21 */
28 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4 22 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
29 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5 23 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
30 srlx %g4, 22, %g3 24 srlx %g4, 22, %g3
31 sllx %g5, 48, %g6 25 sllx %g5, 48, %g6
32 or %g6, %g3, %g6 26 or %g6, %g3, %g6
@@ -90,26 +84,20 @@ sun4v_itlb_load:
90 retry 84 retry
91 85
92sun4v_dtlb_miss: 86sun4v_dtlb_miss:
93 /* Load CPU ID into %g3. */ 87 /* Load MMU Miss base into %g2. */
94 mov SCRATCHPAD_CPUID, %g1 88 ldxa [%g0] ASI_SCRATCHPAD, %g2
95 ldxa [%g1] ASI_SCRATCHPAD, %g3
96 89
97 /* Load UTSB reg into %g1. */ 90 /* Load UTSB reg into %g1. */
91 mov SCRATCHPAD_UTSBREG1, %g1
98 ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1 92 ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1
99 93
100 /* Load &trap_block[smp_processor_id()] into %g2. */
101 sethi %hi(trap_block), %g2
102 or %g2, %lo(trap_block), %g2
103 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
104 add %g2, %g3, %g2
105
106 /* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6. 94 /* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6.
107 * Branch if kernel TLB miss. The kernel TSB and user TSB miss 95 * Branch if kernel TLB miss. The kernel TSB and user TSB miss
108 * code wants the missing virtual address in %g4, so that value 96 * code wants the missing virtual address in %g4, so that value
109 * cannot be modified through the entirety of this handler. 97 * cannot be modified through the entirety of this handler.
110 */ 98 */
111 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 99 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
112 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 100 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
113 srlx %g4, 22, %g3 101 srlx %g4, 22, %g3
114 sllx %g5, 48, %g6 102 sllx %g5, 48, %g6
115 or %g6, %g3, %g6 103 or %g6, %g3, %g6
@@ -169,17 +157,10 @@ sun4v_dtlb_load:
169 retry 157 retry
170 158
171sun4v_dtlb_prot: 159sun4v_dtlb_prot:
172 /* Load CPU ID into %g3. */ 160 /* Load MMU Miss base into %g2. */
173 mov SCRATCHPAD_CPUID, %g1 161 ldxa [%g0] ASI_SCRATCHPAD, %g2
174 ldxa [%g1] ASI_SCRATCHPAD, %g3
175 162
176 /* Load &trap_block[smp_processor_id()] into %g2. */ 163 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
177 sethi %hi(trap_block), %g2
178 or %g2, %lo(trap_block), %g2
179 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
180 add %g2, %g3, %g2
181
182 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g5
183 rdpr %tl, %g1 164 rdpr %tl, %g1
184 cmp %g1, 1 165 cmp %g1, 1
185 bgu,pn %xcc, winfix_trampoline 166 bgu,pn %xcc, winfix_trampoline
@@ -187,35 +168,17 @@ sun4v_dtlb_prot:
187 ba,pt %xcc, sparc64_realfault_common 168 ba,pt %xcc, sparc64_realfault_common
188 mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4 169 mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
189 170
190 /* Called from trap table with &trap_block[smp_processor_id()] in 171 /* Called from trap table with TAG TARGET placed into
191 * %g5 and SCRATCHPAD_UTSBREG1 contents in %g1. 172 * %g6 and SCRATCHPAD_UTSBREG1 contents in %g1.
192 */ 173 */
193sun4v_itsb_miss: 174sun4v_itsb_miss:
194 ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
195 ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
196
197 srlx %g4, 22, %g7
198 sllx %g5, 48, %g6
199 or %g6, %g7, %g6
200 brz,pn %g5, kvmap_itlb_4v
201 nop
202
203 ba,pt %xcc, sun4v_tsb_miss_common 175 ba,pt %xcc, sun4v_tsb_miss_common
204 mov FAULT_CODE_ITLB, %g3 176 mov FAULT_CODE_ITLB, %g3
205 177
206 /* Called from trap table with &trap_block[smp_processor_id()] in 178 /* Called from trap table with TAG TARGET placed into
207 * %g5 and SCRATCHPAD_UTSBREG1 contents in %g1. 179 * %g6 and SCRATCHPAD_UTSBREG1 contents in %g1.
208 */ 180 */
209sun4v_dtsb_miss: 181sun4v_dtsb_miss:
210 ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
211 ldx [%g5 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
212
213 srlx %g4, 22, %g7
214 sllx %g5, 48, %g6
215 or %g6, %g7, %g6
216 brz,pn %g5, kvmap_dtlb_4v
217 nop
218
219 mov FAULT_CODE_DTLB, %g3 182 mov FAULT_CODE_DTLB, %g3
220 183
221 /* Create TSB pointer into %g1. This is something like: 184 /* Create TSB pointer into %g1. This is something like:
@@ -239,15 +202,10 @@ sun4v_tsb_miss_common:
239 202
240 /* Instruction Access Exception, tl0. */ 203 /* Instruction Access Exception, tl0. */
241sun4v_iacc: 204sun4v_iacc:
242 mov SCRATCHPAD_CPUID, %g1 205 ldxa [%g0] ASI_SCRATCHPAD, %g2
243 ldxa [%g1] ASI_SCRATCHPAD, %g3 206 ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
244 sethi %hi(trap_block), %g2 207 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
245 or %g2, %lo(trap_block), %g2 208 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
246 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
247 add %g2, %g3, %g2
248 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3
249 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
250 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
251 sllx %g3, 16, %g3 209 sllx %g3, 16, %g3
252 or %g5, %g3, %g5 210 or %g5, %g3, %g5
253 ba,pt %xcc, etrap 211 ba,pt %xcc, etrap
@@ -260,15 +218,10 @@ sun4v_iacc:
260 218
261 /* Instruction Access Exception, tl1. */ 219 /* Instruction Access Exception, tl1. */
262sun4v_iacc_tl1: 220sun4v_iacc_tl1:
263 mov SCRATCHPAD_CPUID, %g1 221 ldxa [%g0] ASI_SCRATCHPAD, %g2
264 ldxa [%g1] ASI_SCRATCHPAD, %g3 222 ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
265 sethi %hi(trap_block), %g2 223 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
266 or %g2, %lo(trap_block), %g2 224 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
267 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
268 add %g2, %g3, %g2
269 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3
270 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
271 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
272 sllx %g3, 16, %g3 225 sllx %g3, 16, %g3
273 or %g5, %g3, %g5 226 or %g5, %g3, %g5
274 ba,pt %xcc, etraptl1 227 ba,pt %xcc, etraptl1
@@ -281,15 +234,10 @@ sun4v_iacc_tl1:
281 234
282 /* Data Access Exception, tl0. */ 235 /* Data Access Exception, tl0. */
283sun4v_dacc: 236sun4v_dacc:
284 mov SCRATCHPAD_CPUID, %g1 237 ldxa [%g0] ASI_SCRATCHPAD, %g2
285 ldxa [%g1] ASI_SCRATCHPAD, %g3 238 ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
286 sethi %hi(trap_block), %g2 239 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
287 or %g2, %lo(trap_block), %g2 240 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
288 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
289 add %g2, %g3, %g2
290 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
291 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
292 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
293 sllx %g3, 16, %g3 241 sllx %g3, 16, %g3
294 or %g5, %g3, %g5 242 or %g5, %g3, %g5
295 ba,pt %xcc, etrap 243 ba,pt %xcc, etrap
@@ -302,15 +250,10 @@ sun4v_dacc:
302 250
303 /* Data Access Exception, tl1. */ 251 /* Data Access Exception, tl1. */
304sun4v_dacc_tl1: 252sun4v_dacc_tl1:
305 mov SCRATCHPAD_CPUID, %g1 253 ldxa [%g0] ASI_SCRATCHPAD, %g2
306 ldxa [%g1] ASI_SCRATCHPAD, %g3 254 ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
307 sethi %hi(trap_block), %g2 255 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
308 or %g2, %lo(trap_block), %g2 256 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
309 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
310 add %g2, %g3, %g2
311 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
312 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
313 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
314 sllx %g3, 16, %g3 257 sllx %g3, 16, %g3
315 or %g5, %g3, %g5 258 or %g5, %g3, %g5
316 ba,pt %xcc, etraptl1 259 ba,pt %xcc, etraptl1
@@ -323,15 +266,10 @@ sun4v_dacc_tl1:
323 266
324 /* Memory Address Unaligned. */ 267 /* Memory Address Unaligned. */
325sun4v_mna: 268sun4v_mna:
326 mov SCRATCHPAD_CPUID, %g1 269 ldxa [%g0] ASI_SCRATCHPAD, %g2
327 ldxa [%g1] ASI_SCRATCHPAD, %g3
328 sethi %hi(trap_block), %g2
329 or %g2, %lo(trap_block), %g2
330 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
331 add %g2, %g3, %g2
332 mov HV_FAULT_TYPE_UNALIGNED, %g3 270 mov HV_FAULT_TYPE_UNALIGNED, %g3
333 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4 271 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
334 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5 272 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
335 sllx %g3, 16, %g3 273 sllx %g3, 16, %g3
336 or %g5, %g3, %g5 274 or %g5, %g3, %g5
337 275
@@ -359,15 +297,10 @@ sun4v_privact:
359 297
360 /* Unaligned ldd float, tl0. */ 298 /* Unaligned ldd float, tl0. */
361sun4v_lddfmna: 299sun4v_lddfmna:
362 mov SCRATCHPAD_CPUID, %g1 300 ldxa [%g0] ASI_SCRATCHPAD, %g2
363 ldxa [%g1] ASI_SCRATCHPAD, %g3 301 ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
364 sethi %hi(trap_block), %g2 302 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
365 or %g2, %lo(trap_block), %g2 303 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
366 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
367 add %g2, %g3, %g2
368 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
369 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
370 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
371 sllx %g3, 16, %g3 304 sllx %g3, 16, %g3
372 or %g5, %g3, %g5 305 or %g5, %g3, %g5
373 ba,pt %xcc, etrap 306 ba,pt %xcc, etrap
@@ -380,15 +313,10 @@ sun4v_lddfmna:
380 313
381 /* Unaligned std float, tl0. */ 314 /* Unaligned std float, tl0. */
382sun4v_stdfmna: 315sun4v_stdfmna:
383 mov SCRATCHPAD_CPUID, %g1 316 ldxa [%g0] ASI_SCRATCHPAD, %g2
384 ldxa [%g1] ASI_SCRATCHPAD, %g3 317 ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
385 sethi %hi(trap_block), %g2 318 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
386 or %g2, %lo(trap_block), %g2 319 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
387 sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
388 add %g2, %g3, %g2
389 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
390 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
391 ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
392 sllx %g3, 16, %g3 320 sllx %g3, 16, %g3
393 or %g5, %g3, %g5 321 or %g5, %g3, %g5
394 ba,pt %xcc, etrap 322 ba,pt %xcc, etrap
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 11:59:00 -0500