[SPARC64]: Probe D/I/E-cache config and use.

At boot time, determine the D-cache, I-cache and E-cache size and
line-size.  Use them in cache flushes when appropriate.

This change was motivated by discovering that the D-cache on
UltraSparc-IIIi and later are 64K not 32K, and the flushes done by the
Cheetah error handlers were assuming a 32K size.

There are still some pieces of code that are hard coding things and
will need to be fixed up at some point.

While we're here, fix the D-cache and I-cache parity error handlers
to run with interrupts disabled, and when the trap occurs at trap
level > 1 log the event via a counter displayed in /proc/cpuinfo.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 21 insertions, 0 deletions

diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index b4fc6a5462b2..590df5a16f5a 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -93,6 +93,27 @@ void __init smp_store_cpu_info(int id)
         cpu_data(id).pte_cache[1]               = NULL;
         cpu_data(id).pgd_cache                  = NULL;
         cpu_data(id).idle_volume                = 1;
+
+        cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
+                                                      16 * 1024);
+        cpu_data(id).dcache_line_size =
+                prom_getintdefault(cpu_node, "dcache-line-size", 32);
+        cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
+                                                      16 * 1024);
+        cpu_data(id).icache_line_size =
+                prom_getintdefault(cpu_node, "icache-line-size", 32);
+        cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
+                                                      4 * 1024 * 1024);
+        cpu_data(id).ecache_line_size =
+                prom_getintdefault(cpu_node, "ecache-line-size", 64);
+        printk("CPU[%d]: Caches "
+               "D[sz(%d):line_sz(%d)] "
+               "I[sz(%d):line_sz(%d)] "
+               "E[sz(%d):line_sz(%d)]\n",
+               id,
+               cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
+               cpu_data(id).icache_size, cpu_data(id).icache_line_size,
+               cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
 }
 
 static void smp_setup_percpu_timer(void);