[SPARC64]: Probe D/I/E-cache config and use.

At boot time, determine the D-cache, I-cache and E-cache size and
line-size.  Use them in cache flushes when appropriate.

This change was motivated by discovering that the D-cache on
UltraSparc-IIIi and later are 64K not 32K, and the flushes done by the
Cheetah error handlers were assuming a 32K size.

There are still some pieces of code that are hard coding things and
will need to be fixed up at some point.

While we're here, fix the D-cache and I-cache parity error handlers
to run with interrupts disabled, and when the trap occurs at trap
level > 1 log the event via a counter displayed in /proc/cpuinfo.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 8 insertions, 1 deletions

diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
index f4345d837284..8e8baf2354df 100644
--- a/arch/sparc64/kernel/setup.c
+++ b/arch/sparc64/kernel/setup.c
@@ -605,6 +605,9 @@ extern void smp_info(struct seq_file *);
 extern void smp_bogo(struct seq_file *);
 extern void mmu_info(struct seq_file *);
 
+unsigned int dcache_parity_tl1_occurred;
+unsigned int icache_parity_tl1_occurred;
+
 static int show_cpuinfo(struct seq_file *m, void *__unused)
 {
         seq_printf(m, 
@@ -615,6 +618,8 @@ static int show_cpuinfo(struct seq_file *m, void *__unused)
                    "type\t\t: sun4u\n"
                    "ncpus probed\t: %ld\n"
                    "ncpus active\t: %ld\n"
+                   "D$ parity tl1\t: %u\n"
+                   "I$ parity tl1\t: %u\n"
 #ifndef CONFIG_SMP
                    "Cpu0Bogo\t: %lu.%02lu\n"
                    "Cpu0ClkTck\t: %016lx\n"
@@ -627,7 +632,9 @@ static int show_cpuinfo(struct seq_file *m, void *__unused)
                    (prom_prev >> 8) & 0xff,
                    prom_prev & 0xff,
                    (long)num_possible_cpus(),
-                   (long)num_online_cpus()
+                   (long)num_online_cpus(),
+                   dcache_parity_tl1_occurred,
+                   icache_parity_tl1_occurred
 #ifndef CONFIG_SMP
                    , cpu_data(0).udelay_val/(500000/HZ),
                    (cpu_data(0).udelay_val/(5000/HZ)) % 100,