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authorDavid S. Miller <davem@sunset.davemloft.net>2007-06-07 19:58:22 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-06-07 19:59:51 -0400
commitec4d18f219e71ef682fe2d7b9a6d121617fef6d5 (patch)
tree2384d96fc5e4c158f9ef6da34c22af25bf576736 /arch/sparc64/kernel/sbus.c
parent321566c2504445160b18e1508a73081579923a6b (diff)
[SPARC64]: Fix SBUS IRQ regression caused by PCI-E driver.
We used to access the 64-bit IRQ IMAP and ICLR registers of bus controllers 4-bytes in and as a 32-bit register word, since only the low 32-bits were relevant. This seemed like a good idea at the time. But the PCI-E controller requires full 8-byte 64-bit access to these registers, so we switched over to accessing them fully. SBUS was not adjusted properly, which broke interrupts completely. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/sbus.c')
-rw-r--r--arch/sparc64/kernel/sbus.c54
1 files changed, 27 insertions, 27 deletions
diff --git a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c
index 91f6e2a74ad5..a1fd9bcc0b87 100644
--- a/arch/sparc64/kernel/sbus.c
+++ b/arch/sparc64/kernel/sbus.c
@@ -629,29 +629,29 @@ void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
629 * This should conform to both Sunfire/Wildfire server and Fusion 629 * This should conform to both Sunfire/Wildfire server and Fusion
630 * desktop designs. 630 * desktop designs.
631 */ 631 */
632#define SYSIO_IMAP_SLOT0 0x2c04UL 632#define SYSIO_IMAP_SLOT0 0x2c00UL
633#define SYSIO_IMAP_SLOT1 0x2c0cUL 633#define SYSIO_IMAP_SLOT1 0x2c08UL
634#define SYSIO_IMAP_SLOT2 0x2c14UL 634#define SYSIO_IMAP_SLOT2 0x2c10UL
635#define SYSIO_IMAP_SLOT3 0x2c1cUL 635#define SYSIO_IMAP_SLOT3 0x2c18UL
636#define SYSIO_IMAP_SCSI 0x3004UL 636#define SYSIO_IMAP_SCSI 0x3000UL
637#define SYSIO_IMAP_ETH 0x300cUL 637#define SYSIO_IMAP_ETH 0x3008UL
638#define SYSIO_IMAP_BPP 0x3014UL 638#define SYSIO_IMAP_BPP 0x3010UL
639#define SYSIO_IMAP_AUDIO 0x301cUL 639#define SYSIO_IMAP_AUDIO 0x3018UL
640#define SYSIO_IMAP_PFAIL 0x3024UL 640#define SYSIO_IMAP_PFAIL 0x3020UL
641#define SYSIO_IMAP_KMS 0x302cUL 641#define SYSIO_IMAP_KMS 0x3028UL
642#define SYSIO_IMAP_FLPY 0x3034UL 642#define SYSIO_IMAP_FLPY 0x3030UL
643#define SYSIO_IMAP_SHW 0x303cUL 643#define SYSIO_IMAP_SHW 0x3038UL
644#define SYSIO_IMAP_KBD 0x3044UL 644#define SYSIO_IMAP_KBD 0x3040UL
645#define SYSIO_IMAP_MS 0x304cUL 645#define SYSIO_IMAP_MS 0x3048UL
646#define SYSIO_IMAP_SER 0x3054UL 646#define SYSIO_IMAP_SER 0x3050UL
647#define SYSIO_IMAP_TIM0 0x3064UL 647#define SYSIO_IMAP_TIM0 0x3060UL
648#define SYSIO_IMAP_TIM1 0x306cUL 648#define SYSIO_IMAP_TIM1 0x3068UL
649#define SYSIO_IMAP_UE 0x3074UL 649#define SYSIO_IMAP_UE 0x3070UL
650#define SYSIO_IMAP_CE 0x307cUL 650#define SYSIO_IMAP_CE 0x3078UL
651#define SYSIO_IMAP_SBERR 0x3084UL 651#define SYSIO_IMAP_SBERR 0x3080UL
652#define SYSIO_IMAP_PMGMT 0x308cUL 652#define SYSIO_IMAP_PMGMT 0x3088UL
653#define SYSIO_IMAP_GFX 0x3094UL 653#define SYSIO_IMAP_GFX 0x3090UL
654#define SYSIO_IMAP_EUPA 0x309cUL 654#define SYSIO_IMAP_EUPA 0x3098UL
655 655
656#define bogon ((unsigned long) -1) 656#define bogon ((unsigned long) -1)
657static unsigned long sysio_irq_offsets[] = { 657static unsigned long sysio_irq_offsets[] = {
@@ -700,10 +700,10 @@ static unsigned long sysio_irq_offsets[] = {
700 * Interrupt Clear register pointer, SYSIO specific version. 700 * Interrupt Clear register pointer, SYSIO specific version.
701 */ 701 */
702#define SYSIO_ICLR_UNUSED0 0x3400UL 702#define SYSIO_ICLR_UNUSED0 0x3400UL
703#define SYSIO_ICLR_SLOT0 0x340cUL 703#define SYSIO_ICLR_SLOT0 0x3408UL
704#define SYSIO_ICLR_SLOT1 0x344cUL 704#define SYSIO_ICLR_SLOT1 0x3448UL
705#define SYSIO_ICLR_SLOT2 0x348cUL 705#define SYSIO_ICLR_SLOT2 0x3488UL
706#define SYSIO_ICLR_SLOT3 0x34ccUL 706#define SYSIO_ICLR_SLOT3 0x34c8UL
707static unsigned long sysio_imap_to_iclr(unsigned long imap) 707static unsigned long sysio_imap_to_iclr(unsigned long imap)
708{ 708{
709 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0; 709 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;