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authorDavid S. Miller <davem@davemloft.net>2005-05-20 14:40:32 -0400
committerDavid S. Miller <davem@davemloft.net>2005-05-20 14:40:32 -0400
commita228dfd5dc4b92288ea22d427b2bfc48ba5bb8b0 (patch)
treebd3c9a5892a5e3823427c9d614fd6c9aee96c1fb /arch/sparc64/kernel/sbus.c
parent37e0915b701281182cea9fc90e894d10addf134a (diff)
[SPARC64]: Fix bad performance side effect of strbuf timeout changes.
The recent change to add a timeout to strbuf flushing had a negative performance impact. The udelay()'s are too long, and they were done in the wrong order wrt. the register read checks. Fix both, and things are happy again. There are more possible improvements in this area. In fact, PCI streaming buffer flushing seems to be part of the bottleneck in network receive performance on my SunBlade1000 box. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/sbus.c')
-rw-r--r--arch/sparc64/kernel/sbus.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c
index d3eca98e1fe7..76ea6455433f 100644
--- a/arch/sparc64/kernel/sbus.c
+++ b/arch/sparc64/kernel/sbus.c
@@ -133,12 +133,12 @@ static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long
133 iommu->strbuf_regs + STRBUF_FSYNC); 133 iommu->strbuf_regs + STRBUF_FSYNC);
134 upa_readq(iommu->sbus_control_reg); 134 upa_readq(iommu->sbus_control_reg);
135 135
136 limit = 10000; 136 limit = 100000;
137 while (iommu->strbuf_flushflag == 0UL) { 137 while (iommu->strbuf_flushflag == 0UL) {
138 limit--; 138 limit--;
139 if (!limit) 139 if (!limit)
140 break; 140 break;
141 udelay(10); 141 udelay(1);
142 membar("#LoadLoad"); 142 membar("#LoadLoad");
143 } 143 }
144 if (!limit) 144 if (!limit)