[SPARC64]: Fix bogus flush instruction usage.

Some of the trap code was still assuming that alternate
global %g6 was hard coded with current_thread_info().
Let's just consistently flush at KERNBASE when we need
a pipeline synchronization.  That's locked into the TLB
and will always work.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 2 insertions, 1 deletions

diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index 5a62ec5d531c..89794ebdcbcf 100644
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -259,7 +259,8 @@ rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
                 ldx                     [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
                 or                      %l0, %l1, %l0
                 stxa                    %l0, [%l7] ASI_DMMU
-                flush                   %g6
+                sethi                   %hi(KERNBASE), %l7
+                flush                   %l7
                 rdpr                    %wstate, %l1
                 rdpr                    %otherwin, %l2
                 srl                     %l1, 3, %l1