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authorDavid S. Miller <davem@sunset.davemloft.net>2007-02-10 20:41:02 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2007-02-11 02:50:37 -0500
commit35a17eb6a87c9ceb0d35dcb51f464fe6faf584ab (patch)
tree7f56095a56e9f62dca7514cdfe781739548011f5 /arch/sparc64/kernel/pci_sun4v_asm.S
parent68c921869491c119142612fa5796c9f8b4e9970b (diff)
[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities much better. MSIs are assosciated with MSI Queues. MSI Queues generate interrupts when any MSI assosciated with it is signalled. This suggests a two-tiered IRQ dispatch scheme: MSI Queue interrupt --> queue interrupt handler MSI dispatch --> driver interrupt handler But we just get one-level under Linux currently. What I'd like to do is possibly stick the IRQ actions into a per-MSI-Queue data structure, and dispatch them form there, but the generic IRQ layer doesn't provide a way to do that right now. So, the current kludge is to "ACK" the interrupt by processing the MSI Queue data structures and ACK'ing them, then we run the actual handler like normal. We are wasting a lot of useful information, for example the MSI data and address are provided with ever MSI, as well as a system tick if available. If we could pass this into the IRQ handler it could help with certain things, in particular for PCI-Express error messages. The MSI entries on sparc64 also tell you exactly which bus/device/fn sent the MSI, which would be great for error handling when no registered IRQ handler can service the interrupt. We override the disable/enable IRQ chip methods in sun4v_msi, so we have to call {mask,unmask}_msi_irq() directly from there. This is another ugly wart. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_sun4v_asm.S')
-rw-r--r--arch/sparc64/kernel/pci_sun4v_asm.S266
1 files changed, 266 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/pci_sun4v_asm.S b/arch/sparc64/kernel/pci_sun4v_asm.S
index 6604fdbf746c..ecb81f389b06 100644
--- a/arch/sparc64/kernel/pci_sun4v_asm.S
+++ b/arch/sparc64/kernel/pci_sun4v_asm.S
@@ -93,3 +93,269 @@ pci_sun4v_config_put:
93 mov -1, %o1 93 mov -1, %o1
941: retl 941: retl
95 mov %o1, %o0 95 mov %o1, %o0
96
97 /* %o0: devhandle
98 * %o1: msiqid
99 * %o2: msiq phys address
100 * %o3: num entries
101 *
102 * returns %o0: status
103 *
104 * status will be zero if the operation completed
105 * successfully, else -1 if not
106 */
107 .globl pci_sun4v_msiq_conf
108pci_sun4v_msiq_conf:
109 mov HV_FAST_PCI_MSIQ_CONF, %o5
110 ta HV_FAST_TRAP
111 retl
112 mov %o0, %o0
113
114 /* %o0: devhandle
115 * %o1: msiqid
116 * %o2: &msiq_phys_addr
117 * %o3: &msiq_num_entries
118 *
119 * returns %o0: status
120 */
121 .globl pci_sun4v_msiq_info
122pci_sun4v_msiq_info:
123 mov %o2, %o4
124 mov HV_FAST_PCI_MSIQ_INFO, %o5
125 ta HV_FAST_TRAP
126 stx %o1, [%o4]
127 stx %o2, [%o3]
128 retl
129 mov %o0, %o0
130
131 /* %o0: devhandle
132 * %o1: msiqid
133 * %o2: &valid
134 *
135 * returns %o0: status
136 */
137 .globl pci_sun4v_msiq_getvalid
138pci_sun4v_msiq_getvalid:
139 mov HV_FAST_PCI_MSIQ_GETVALID, %o5
140 ta HV_FAST_TRAP
141 stx %o1, [%o2]
142 retl
143 mov %o0, %o0
144
145 /* %o0: devhandle
146 * %o1: msiqid
147 * %o2: valid
148 *
149 * returns %o0: status
150 */
151 .globl pci_sun4v_msiq_setvalid
152pci_sun4v_msiq_setvalid:
153 mov HV_FAST_PCI_MSIQ_SETVALID, %o5
154 ta HV_FAST_TRAP
155 retl
156 mov %o0, %o0
157
158 /* %o0: devhandle
159 * %o1: msiqid
160 * %o2: &state
161 *
162 * returns %o0: status
163 */
164 .globl pci_sun4v_msiq_getstate
165pci_sun4v_msiq_getstate:
166 mov HV_FAST_PCI_MSIQ_GETSTATE, %o5
167 ta HV_FAST_TRAP
168 stx %o1, [%o2]
169 retl
170 mov %o0, %o0
171
172 /* %o0: devhandle
173 * %o1: msiqid
174 * %o2: state
175 *
176 * returns %o0: status
177 */
178 .globl pci_sun4v_msiq_setstate
179pci_sun4v_msiq_setstate:
180 mov HV_FAST_PCI_MSIQ_SETSTATE, %o5
181 ta HV_FAST_TRAP
182 retl
183 mov %o0, %o0
184
185 /* %o0: devhandle
186 * %o1: msiqid
187 * %o2: &head
188 *
189 * returns %o0: status
190 */
191 .globl pci_sun4v_msiq_gethead
192pci_sun4v_msiq_gethead:
193 mov HV_FAST_PCI_MSIQ_GETHEAD, %o5
194 ta HV_FAST_TRAP
195 stx %o1, [%o2]
196 retl
197 mov %o0, %o0
198
199 /* %o0: devhandle
200 * %o1: msiqid
201 * %o2: head
202 *
203 * returns %o0: status
204 */
205 .globl pci_sun4v_msiq_sethead
206pci_sun4v_msiq_sethead:
207 mov HV_FAST_PCI_MSIQ_SETHEAD, %o5
208 ta HV_FAST_TRAP
209 retl
210 mov %o0, %o0
211
212 /* %o0: devhandle
213 * %o1: msiqid
214 * %o2: &tail
215 *
216 * returns %o0: status
217 */
218 .globl pci_sun4v_msiq_gettail
219pci_sun4v_msiq_gettail:
220 mov HV_FAST_PCI_MSIQ_GETTAIL, %o5
221 ta HV_FAST_TRAP
222 stx %o1, [%o2]
223 retl
224 mov %o0, %o0
225
226 /* %o0: devhandle
227 * %o1: msinum
228 * %o2: &valid
229 *
230 * returns %o0: status
231 */
232 .globl pci_sun4v_msi_getvalid
233pci_sun4v_msi_getvalid:
234 mov HV_FAST_PCI_MSI_GETVALID, %o5
235 ta HV_FAST_TRAP
236 stx %o1, [%o2]
237 retl
238 mov %o0, %o0
239
240 /* %o0: devhandle
241 * %o1: msinum
242 * %o2: valid
243 *
244 * returns %o0: status
245 */
246 .globl pci_sun4v_msi_setvalid
247pci_sun4v_msi_setvalid:
248 mov HV_FAST_PCI_MSI_SETVALID, %o5
249 ta HV_FAST_TRAP
250 retl
251 mov %o0, %o0
252
253 /* %o0: devhandle
254 * %o1: msinum
255 * %o2: &msiq
256 *
257 * returns %o0: status
258 */
259 .globl pci_sun4v_msi_getmsiq
260pci_sun4v_msi_getmsiq:
261 mov HV_FAST_PCI_MSI_GETMSIQ, %o5
262 ta HV_FAST_TRAP
263 stx %o1, [%o2]
264 retl
265 mov %o0, %o0
266
267 /* %o0: devhandle
268 * %o1: msinum
269 * %o2: msitype
270 * %o3: msiq
271 *
272 * returns %o0: status
273 */
274 .globl pci_sun4v_msi_setmsiq
275pci_sun4v_msi_setmsiq:
276 mov HV_FAST_PCI_MSI_SETMSIQ, %o5
277 ta HV_FAST_TRAP
278 retl
279 mov %o0, %o0
280
281 /* %o0: devhandle
282 * %o1: msinum
283 * %o2: &state
284 *
285 * returns %o0: status
286 */
287 .globl pci_sun4v_msi_getstate
288pci_sun4v_msi_getstate:
289 mov HV_FAST_PCI_MSI_GETSTATE, %o5
290 ta HV_FAST_TRAP
291 stx %o1, [%o2]
292 retl
293 mov %o0, %o0
294
295 /* %o0: devhandle
296 * %o1: msinum
297 * %o2: state
298 *
299 * returns %o0: status
300 */
301 .globl pci_sun4v_msi_setstate
302pci_sun4v_msi_setstate:
303 mov HV_FAST_PCI_MSI_SETSTATE, %o5
304 ta HV_FAST_TRAP
305 retl
306 mov %o0, %o0
307
308 /* %o0: devhandle
309 * %o1: msinum
310 * %o2: &msiq
311 *
312 * returns %o0: status
313 */
314 .globl pci_sun4v_msg_getmsiq
315pci_sun4v_msg_getmsiq:
316 mov HV_FAST_PCI_MSG_GETMSIQ, %o5
317 ta HV_FAST_TRAP
318 stx %o1, [%o2]
319 retl
320 mov %o0, %o0
321
322 /* %o0: devhandle
323 * %o1: msinum
324 * %o2: msiq
325 *
326 * returns %o0: status
327 */
328 .globl pci_sun4v_msg_setmsiq
329pci_sun4v_msg_setmsiq:
330 mov HV_FAST_PCI_MSG_SETMSIQ, %o5
331 ta HV_FAST_TRAP
332 retl
333 mov %o0, %o0
334
335 /* %o0: devhandle
336 * %o1: msinum
337 * %o2: &valid
338 *
339 * returns %o0: status
340 */
341 .globl pci_sun4v_msg_getvalid
342pci_sun4v_msg_getvalid:
343 mov HV_FAST_PCI_MSG_GETVALID, %o5
344 ta HV_FAST_TRAP
345 stx %o1, [%o2]
346 retl
347 mov %o0, %o0
348
349 /* %o0: devhandle
350 * %o1: msinum
351 * %o2: valid
352 *
353 * returns %o0: status
354 */
355 .globl pci_sun4v_msg_setvalid
356pci_sun4v_msg_setvalid:
357 mov HV_FAST_PCI_MSG_SETVALID, %o5
358 ta HV_FAST_TRAP
359 retl
360 mov %o0, %o0
361