[SPARC64] PCI: Consolidate PCI access code into pci_common.c

All the sun4u controllers do the same thing to compute the physical
I/O address to poke, and we can move the sun4v code into this common
location too.

This one needs a bit of testing, in particular the Sabre code had some
funny stuff that would break up u16 and/or u32 accesses into pieces
and I didn't think that was needed any more.  If it is we need to find
out why and add back code to do it again.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 2 insertions, 120 deletions

diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index e375d72b8eed..ae76898bbe2b 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -104,125 +104,6 @@ static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
                  SCHIZO_CONFIG_ENCODE(bus, devfn, where));
 }
 
-/* Just make sure the bus number is in range.  */
-static int schizo_out_of_range(struct pci_pbm_info *pbm,
-                               unsigned char bus,
-                               unsigned char devfn)
-{
-        if (bus < pbm->pci_first_busno ||
-            bus > pbm->pci_last_busno)
-                return 1;
-        return 0;
-}
-
-/* SCHIZO PCI configuration space accessors. */
-
-static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
-                               int where, int size, u32 *value)
-{
-        struct pci_pbm_info *pbm = bus_dev->sysdata;
-        unsigned char bus = bus_dev->number;
-        u32 *addr;
-        u16 tmp16;
-        u8 tmp8;
-
-        if (bus_dev == pbm->pci_bus && devfn == 0x00)
-                return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
-                                                    size, value);
-        switch (size) {
-        case 1:
-                *value = 0xff;
-                break;
-        case 2:
-                *value = 0xffff;
-                break;
-        case 4:
-                *value = 0xffffffff;
-                break;
-        }
-
-        addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
-        if (!addr)
-                return PCIBIOS_SUCCESSFUL;
-
-        if (schizo_out_of_range(pbm, bus, devfn))
-                return PCIBIOS_SUCCESSFUL;
-        switch (size) {
-        case 1:
-                pci_config_read8((u8 *)addr, &tmp8);
-                *value = tmp8;
-                break;
-
-        case 2:
-                if (where & 0x01) {
-                        printk("pci_read_config_word: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_read16((u16 *)addr, &tmp16);
-                *value = tmp16;
-                break;
-
-        case 4:
-                if (where & 0x03) {
-                        printk("pci_read_config_dword: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_read32(addr, value);
-                break;
-        }
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
-                                int where, int size, u32 value)
-{
-        struct pci_pbm_info *pbm = bus_dev->sysdata;
-        unsigned char bus = bus_dev->number;
-        u32 *addr;
-
-        if (bus_dev == pbm->pci_bus && devfn == 0x00)
-                return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
-                                                     size, value);
-        addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
-        if (!addr)
-                return PCIBIOS_SUCCESSFUL;
-
-        if (schizo_out_of_range(pbm, bus, devfn))
-                return PCIBIOS_SUCCESSFUL;
-
-        switch (size) {
-        case 1:
-                pci_config_write8((u8 *)addr, value);
-                break;
-
-        case 2:
-                if (where & 0x01) {
-                        printk("pci_write_config_word: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_write16((u16 *)addr, value);
-                break;
-
-        case 4:
-                if (where & 0x03) {
-                        printk("pci_write_config_dword: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-
-                pci_config_write32(addr, value);
-        }
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops schizo_ops = {
-        .read =         schizo_read_pci_cfg,
-        .write =        schizo_write_pci_cfg,
-};
-
 /* SCHIZO error handling support. */
 enum schizo_error_type {
         UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
@@ -1494,7 +1375,8 @@ static void schizo_pbm_init(struct pci_controller_info *p,
         pci_pbm_root = pbm;
 
         pbm->scan_bus = schizo_scan_bus;
-        pbm->pci_ops = &schizo_ops;
+        pbm->pci_ops = &sun4u_pci_ops;
+        pbm->config_space_reg_bits = 8;
 
         pbm->index = pci_num_pbms++;