aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sparc64/kernel/pci_schizo.c
diff options
context:
space:
mode:
authorDavid S. Miller <davem@sunset.davemloft.net>2007-05-08 02:06:27 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-05-08 19:41:24 -0400
commit34768bc8329194b14e42ee408a84edfa40059046 (patch)
tree3fff53138966f3a58e796a71c19a3b75de86fbf7 /arch/sparc64/kernel/pci_schizo.c
parent5a4a3e592d0d66653297049373caa7ac5b4febe0 (diff)
[SPARC64] PCI: Use root list of pbm's instead of pci_controller_info's
The idea is to move more and more things into the pbm, with the eventual goal of eliminating the pci_controller_info entirely as there really isn't any need for it. This stage of the transformations requires some reworking of the PCI error interrupt handling. It might be tricky to get rid of the pci_controller_info parenting for a few reasons: 1) When we get an uncorrectable or correctable error we want to interrogate the IOMMU and streaming cache of both PBMs for error status. These errors come from the UPA front-end which is shared between the two PBM PCI bus segments. Historically speaking this is why I choose the datastructure hierarchy of pci_controller_info-->pci_pbm_info 2) The probing does a portid/devhandle match to look for the 'other' pbm, but this is entirely an artifact and can be eliminated trivially. What we could do to solve #1 is to have a "buddy" pointer from one pbm to another. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_schizo.c')
-rw-r--r--arch/sparc64/kernel/pci_schizo.c256
1 files changed, 89 insertions, 167 deletions
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
index c0a6a3866e2f..4ebdcbd5262a 100644
--- a/arch/sparc64/kernel/pci_schizo.c
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -238,25 +238,6 @@ static unsigned long stc_line_buf[16];
238#define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ 238#define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
239#define SCHIZO_SERR_INO 0x34 /* Safari interface error */ 239#define SCHIZO_SERR_INO 0x34 /* Safari interface error */
240 240
241struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
242{
243 ino &= IMAP_INO;
244 if (p->pbm_A.ino_bitmap & (1UL << ino))
245 return &p->pbm_A;
246 if (p->pbm_B.ino_bitmap & (1UL << ino))
247 return &p->pbm_B;
248
249 printk("PCI%d: No ino_bitmap entry for ino[%x], bitmaps "
250 "PBM_A[%016lx] PBM_B[%016lx]",
251 p->index, ino,
252 p->pbm_A.ino_bitmap,
253 p->pbm_B.ino_bitmap);
254 printk("PCI%d: Using PBM_A, report this problem immediately.\n",
255 p->index);
256
257 return &p->pbm_A;
258}
259
260#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ 241#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
261#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ 242#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
262#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ 243#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
@@ -522,9 +503,10 @@ static void schizo_check_iommu_error(struct pci_controller_info *p,
522 503
523static irqreturn_t schizo_ue_intr(int irq, void *dev_id) 504static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
524{ 505{
525 struct pci_controller_info *p = dev_id; 506 struct pci_pbm_info *pbm = dev_id;
526 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFSR; 507 struct pci_controller_info *p = pbm->parent;
527 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFAR; 508 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
509 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
528 unsigned long afsr, afar, error_bits; 510 unsigned long afsr, afar, error_bits;
529 int reported, limit; 511 int reported, limit;
530 512
@@ -610,9 +592,10 @@ static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
610 592
611static irqreturn_t schizo_ce_intr(int irq, void *dev_id) 593static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
612{ 594{
613 struct pci_controller_info *p = dev_id; 595 struct pci_pbm_info *pbm = dev_id;
614 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFSR; 596 struct pci_controller_info *p = pbm->parent;
615 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFAR; 597 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
598 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
616 unsigned long afsr, afar, error_bits; 599 unsigned long afsr, afar, error_bits;
617 int reported, limit; 600 int reported, limit;
618 601
@@ -940,11 +923,12 @@ static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
940 */ 923 */
941static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id) 924static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
942{ 925{
943 struct pci_controller_info *p = dev_id; 926 struct pci_pbm_info *pbm = dev_id;
927 struct pci_controller_info *p = pbm->parent;
944 u64 errlog; 928 u64 errlog;
945 929
946 errlog = schizo_read(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG); 930 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
947 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG, 931 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG,
948 errlog & ~(SAFARI_ERRLOG_ERROUT)); 932 errlog & ~(SAFARI_ERRLOG_ERROUT));
949 933
950 if (!(errlog & BUS_ERROR_UNMAP)) { 934 if (!(errlog & BUS_ERROR_UNMAP)) {
@@ -972,6 +956,16 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
972#define SCHIZO_SAFARI_IRQCTRL 0x10010UL 956#define SCHIZO_SAFARI_IRQCTRL 0x10010UL
973#define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL 957#define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
974 958
959static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
960{
961 ino &= IMAP_INO;
962
963 if (pbm->ino_bitmap & (1UL << ino))
964 return 1;
965
966 return 0;
967}
968
975/* How the Tomatillo IRQs are routed around is pure guesswork here. 969/* How the Tomatillo IRQs are routed around is pure guesswork here.
976 * 970 *
977 * All the Tomatillo devices I see in prtconf dumps seem to have only 971 * All the Tomatillo devices I see in prtconf dumps seem to have only
@@ -986,10 +980,9 @@ static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
986 * PCI bus units of the same Tomatillo. I still have not really 980 * PCI bus units of the same Tomatillo. I still have not really
987 * figured this out... 981 * figured this out...
988 */ 982 */
989static void tomatillo_register_error_handlers(struct pci_controller_info *p) 983static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
990{ 984{
991 struct pci_pbm_info *pbm; 985 struct of_device *op = of_find_device_by_node(pbm->prom_node);
992 struct of_device *op;
993 u64 tmp, err_mask, err_no_mask; 986 u64 tmp, err_mask, err_no_mask;
994 987
995 /* Tomatillo IRQ property layout is: 988 /* Tomatillo IRQ property layout is:
@@ -1000,44 +993,27 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
1000 * 4: POWER FAIL? 993 * 4: POWER FAIL?
1001 */ 994 */
1002 995
1003 pbm = pbm_for_ino(p, SCHIZO_UE_INO); 996 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO))
1004 op = of_find_device_by_node(pbm->prom_node); 997 request_irq(op->irqs[1], schizo_ue_intr, 0,
1005 if (op) 998 "TOMATILLO_UE", pbm);
1006 request_irq(op->irqs[1], schizo_ue_intr, IRQF_SHARED,
1007 "TOMATILLO_UE", p);
1008
1009 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1010 op = of_find_device_by_node(pbm->prom_node);
1011 if (op)
1012 request_irq(op->irqs[2], schizo_ce_intr, IRQF_SHARED,
1013 "TOMATILLO CE", p);
1014
1015 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1016 op = of_find_device_by_node(pbm->prom_node);
1017 if (op)
1018 request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED,
1019 "TOMATILLO PCIERR-A", pbm);
1020
1021
1022 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1023 op = of_find_device_by_node(pbm->prom_node);
1024 if (op)
1025 request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED,
1026 "TOMATILLO PCIERR-B", pbm);
1027
1028 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1029 op = of_find_device_by_node(pbm->prom_node);
1030 if (op)
1031 request_irq(op->irqs[3], schizo_safarierr_intr, IRQF_SHARED,
1032 "TOMATILLO SERR", p);
1033 999
1034 /* Enable UE and CE interrupts for controller. */ 1000 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO))
1035 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, 1001 request_irq(op->irqs[2], schizo_ce_intr, 0,
1036 (SCHIZO_ECCCTRL_EE | 1002 "TOMATILLO_CE", pbm);
1037 SCHIZO_ECCCTRL_UE | 1003
1038 SCHIZO_ECCCTRL_CE)); 1004 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO))
1005 request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1006 "TOMATILLO_PCIERR", pbm);
1007 else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO))
1008 request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1009 "TOMATILLO_PCIERR", pbm);
1039 1010
1040 schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL, 1011 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO))
1012 request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1013 "TOMATILLO_SERR", pbm);
1014
1015 /* Enable UE and CE interrupts for controller. */
1016 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1041 (SCHIZO_ECCCTRL_EE | 1017 (SCHIZO_ECCCTRL_EE |
1042 SCHIZO_ECCCTRL_UE | 1018 SCHIZO_ECCCTRL_UE |
1043 SCHIZO_ECCCTRL_CE)); 1019 SCHIZO_ECCCTRL_CE));
@@ -1053,15 +1029,10 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
1053 1029
1054 err_no_mask = SCHIZO_PCICTRL_DTO_ERR; 1030 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
1055 1031
1056 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL); 1032 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1057 tmp |= err_mask;
1058 tmp &= ~err_no_mask;
1059 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1060
1061 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1062 tmp |= err_mask; 1033 tmp |= err_mask;
1063 tmp &= ~err_no_mask; 1034 tmp &= ~err_no_mask;
1064 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp); 1035 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1065 1036
1066 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1037 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1067 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1038 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
@@ -1070,8 +1041,7 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
1070 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 1041 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1071 SCHIZO_PCIAFSR_STTO); 1042 SCHIZO_PCIAFSR_STTO);
1072 1043
1073 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask); 1044 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1074 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1075 1045
1076 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | 1046 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
1077 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | 1047 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
@@ -1083,21 +1053,16 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
1083 BUS_ERROR_APERR | BUS_ERROR_UNMAP | 1053 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
1084 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); 1054 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
1085 1055
1086 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL, 1056 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1087 (SCHIZO_SAFERRCTRL_EN | err_mask));
1088 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1089 (SCHIZO_SAFERRCTRL_EN | err_mask)); 1057 (SCHIZO_SAFERRCTRL_EN | err_mask));
1090 1058
1091 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL, 1059 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL,
1092 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1093 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1094 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); 1060 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1095} 1061}
1096 1062
1097static void schizo_register_error_handlers(struct pci_controller_info *p) 1063static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1098{ 1064{
1099 struct pci_pbm_info *pbm; 1065 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1100 struct of_device *op;
1101 u64 tmp, err_mask, err_no_mask; 1066 u64 tmp, err_mask, err_no_mask;
1102 1067
1103 /* Schizo IRQ property layout is: 1068 /* Schizo IRQ property layout is:
@@ -1108,39 +1073,27 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
1108 * 4: POWER FAIL? 1073 * 4: POWER FAIL?
1109 */ 1074 */
1110 1075
1111 pbm = pbm_for_ino(p, SCHIZO_UE_INO); 1076 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO))
1112 op = of_find_device_by_node(pbm->prom_node); 1077 request_irq(op->irqs[1], schizo_ue_intr, 0,
1113 if (op) 1078 "SCHIZO_UE", pbm);
1114 request_irq(op->irqs[1], schizo_ue_intr, IRQF_SHARED, 1079
1115 "SCHIZO_UE", p); 1080 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO))
1116 1081 request_irq(op->irqs[2], schizo_ce_intr, 0,
1117 pbm = pbm_for_ino(p, SCHIZO_CE_INO); 1082 "SCHIZO_CE", pbm);
1118 op = of_find_device_by_node(pbm->prom_node); 1083
1119 if (op) 1084 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO))
1120 request_irq(op->irqs[2], schizo_ce_intr, IRQF_SHARED, 1085 request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1121 "SCHIZO CE", p); 1086 "SCHIZO_PCIERR", pbm);
1122 1087 else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO))
1123 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); 1088 request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1124 op = of_find_device_by_node(pbm->prom_node); 1089 "SCHIZO_PCIERR", pbm);
1125 if (op) 1090
1126 request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED, 1091 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO))
1127 "SCHIZO PCIERR-A", pbm); 1092 request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1128 1093 "SCHIZO_SERR", pbm);
1129
1130 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1131 op = of_find_device_by_node(pbm->prom_node);
1132 if (op)
1133 request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED,
1134 "SCHIZO PCIERR-B", pbm);
1135
1136 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1137 op = of_find_device_by_node(pbm->prom_node);
1138 if (op)
1139 request_irq(op->irqs[3], schizo_safarierr_intr, IRQF_SHARED,
1140 "SCHIZO SERR", p);
1141 1094
1142 /* Enable UE and CE interrupts for controller. */ 1095 /* Enable UE and CE interrupts for controller. */
1143 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, 1096 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1144 (SCHIZO_ECCCTRL_EE | 1097 (SCHIZO_ECCCTRL_EE |
1145 SCHIZO_ECCCTRL_UE | 1098 SCHIZO_ECCCTRL_UE |
1146 SCHIZO_ECCCTRL_CE)); 1099 SCHIZO_ECCCTRL_CE));
@@ -1159,25 +1112,12 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
1159 /* Enable PCI Error interrupts and clear error 1112 /* Enable PCI Error interrupts and clear error
1160 * bits for each PBM. 1113 * bits for each PBM.
1161 */ 1114 */
1162 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL); 1115 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1163 tmp |= err_mask;
1164 tmp &= ~err_no_mask;
1165 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1166
1167 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR,
1168 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1169 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1170 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1171 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1172 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1173 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1174
1175 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1176 tmp |= err_mask; 1116 tmp |= err_mask;
1177 tmp &= ~err_no_mask; 1117 tmp &= ~err_no_mask;
1178 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp); 1118 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1179 1119
1180 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, 1120 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR,
1181 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1121 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1182 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1122 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1183 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 1123 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
@@ -1210,11 +1150,8 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
1210 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); 1150 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1211#endif 1151#endif
1212 1152
1213 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL, 1153 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1214 (SCHIZO_SAFERRCTRL_EN | err_mask)); 1154 (SCHIZO_SAFERRCTRL_EN | err_mask));
1215
1216 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1217 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1218} 1155}
1219 1156
1220static void pbm_config_busmastering(struct pci_pbm_info *pbm) 1157static void pbm_config_busmastering(struct pci_pbm_info *pbm)
@@ -1234,27 +1171,19 @@ static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1234 pci_config_write8(addr, 64); 1171 pci_config_write8(addr, 64);
1235} 1172}
1236 1173
1237static void schizo_scan_bus(struct pci_controller_info *p) 1174static void schizo_scan_bus(struct pci_pbm_info *pbm)
1238{ 1175{
1239 pbm_config_busmastering(&p->pbm_B); 1176 pbm_config_busmastering(pbm);
1240 p->pbm_B.is_66mhz_capable = 1177 pbm->is_66mhz_capable =
1241 (of_find_property(p->pbm_B.prom_node, "66mhz-capable", NULL) 1178 (of_find_property(pbm->prom_node, "66mhz-capable", NULL)
1242 != NULL);
1243 pbm_config_busmastering(&p->pbm_A);
1244 p->pbm_A.is_66mhz_capable =
1245 (of_find_property(p->pbm_A.prom_node, "66mhz-capable", NULL)
1246 != NULL); 1179 != NULL);
1247 1180
1248 p->pbm_B.pci_bus = pci_scan_one_pbm(&p->pbm_B); 1181 pbm->pci_bus = pci_scan_one_pbm(pbm);
1249 p->pbm_A.pci_bus = pci_scan_one_pbm(&p->pbm_A);
1250 1182
1251 /* After the PCI bus scan is complete, we can register 1183 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1252 * the error interrupt handlers. 1184 tomatillo_register_error_handlers(pbm);
1253 */
1254 if (p->pbm_B.chip_type == PBM_CHIP_TYPE_TOMATILLO)
1255 tomatillo_register_error_handlers(p);
1256 else 1185 else
1257 schizo_register_error_handlers(p); 1186 schizo_register_error_handlers(pbm);
1258} 1187}
1259 1188
1260#define SCHIZO_STRBUF_CONTROL (0x02800UL) 1189#define SCHIZO_STRBUF_CONTROL (0x02800UL)
@@ -1529,6 +1458,11 @@ static void schizo_pbm_init(struct pci_controller_info *p,
1529 else 1458 else
1530 pbm = &p->pbm_B; 1459 pbm = &p->pbm_B;
1531 1460
1461 pbm->next = pci_pbm_root;
1462 pci_pbm_root = pbm;
1463
1464 pbm->scan_bus = schizo_scan_bus;
1465
1532 pbm->portid = portid; 1466 pbm->portid = portid;
1533 pbm->parent = p; 1467 pbm->parent = p;
1534 pbm->prom_node = dp; 1468 pbm->prom_node = dp;
@@ -1572,23 +1506,15 @@ static inline int portid_compare(u32 x, u32 y, int chip_type)
1572static void __schizo_init(struct device_node *dp, char *model_name, int chip_type) 1506static void __schizo_init(struct device_node *dp, char *model_name, int chip_type)
1573{ 1507{
1574 struct pci_controller_info *p; 1508 struct pci_controller_info *p;
1509 struct pci_pbm_info *pbm;
1575 struct iommu *iommu; 1510 struct iommu *iommu;
1576 u32 portid; 1511 u32 portid;
1577 1512
1578 portid = of_getintprop_default(dp, "portid", 0xff); 1513 portid = of_getintprop_default(dp, "portid", 0xff);
1579 1514
1580 for (p = pci_controller_root; p; p = p->next) { 1515 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1581 struct pci_pbm_info *pbm;
1582
1583 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
1584 continue;
1585
1586 pbm = (p->pbm_A.prom_node ?
1587 &p->pbm_A :
1588 &p->pbm_B);
1589
1590 if (portid_compare(pbm->portid, portid, chip_type)) { 1516 if (portid_compare(pbm->portid, portid, chip_type)) {
1591 schizo_pbm_init(p, dp, portid, chip_type); 1517 schizo_pbm_init(pbm->parent, dp, portid, chip_type);
1592 return; 1518 return;
1593 } 1519 }
1594 } 1520 }
@@ -1609,11 +1535,7 @@ static void __schizo_init(struct device_node *dp, char *model_name, int chip_typ
1609 1535
1610 p->pbm_B.iommu = iommu; 1536 p->pbm_B.iommu = iommu;
1611 1537
1612 p->next = pci_controller_root;
1613 pci_controller_root = p;
1614
1615 p->index = pci_num_controllers++; 1538 p->index = pci_num_controllers++;
1616 p->scan_bus = schizo_scan_bus;
1617 p->pci_ops = &schizo_ops; 1539 p->pci_ops = &schizo_ops;
1618 1540
1619 /* Like PSYCHO we have a 2GB aligned area for memory space. */ 1541 /* Like PSYCHO we have a 2GB aligned area for memory space. */