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authorDavid S. Miller <davem@davemloft.net>2005-05-31 19:57:59 -0400
committerDavid S. Miller <davem@davemloft.net>2005-05-31 19:57:59 -0400
commit7c963ad1d113790a8c723a178988b675868f3abe (patch)
tree2e1cc54795aeca06a11801636737901ba71a2ed8 /arch/sparc64/kernel/pci_sabre.c
parent2e3e80c2b75e3815a0160cbd23d4fdb767d66b35 (diff)
[SPARC64]: Fix streaming buffer flushing on PCI and SBUS.
Firstly, if the direction is TODEVICE, then dirty data in the streaming cache is impossible so we can elide the flush-flag synchronization in that case. Next, the context allocator is broken. It is highly likely that contexts get used multiple times for different dma mappings, which confuses the strbuf flushing code and makes it run inefficiently. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_sabre.c')
-rw-r--r--arch/sparc64/kernel/pci_sabre.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 5525d1ec4af8..53d333b4a4e8 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -1265,7 +1265,7 @@ static void __init sabre_iommu_init(struct pci_controller_info *p,
1265 1265
1266 /* Setup initial software IOMMU state. */ 1266 /* Setup initial software IOMMU state. */
1267 spin_lock_init(&iommu->lock); 1267 spin_lock_init(&iommu->lock);
1268 iommu->iommu_cur_ctx = 0; 1268 iommu->ctx_lowest_free = 1;
1269 1269
1270 /* Register addresses. */ 1270 /* Register addresses. */
1271 iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL; 1271 iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;