[SPARC64] PCI: Consolidate PCI access code into pci_common.c

All the sun4u controllers do the same thing to compute the physical
I/O address to poke, and we can move the sun4v code into this common
location too.

This one needs a bit of testing, in particular the Sabre code had some
funny stuff that would break up u16 and/or u32 accesses into pieces
and I didn't think that was needed any more.  If it is we need to find
out why and add back code to do it again.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 2 insertions, 286 deletions

diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 4cefe6e83b24..e2377796de89 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -205,294 +205,9 @@
 #define SABRE_MEMSPACE          0x100000000UL
 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 
-/* UltraSparc-IIi Programmer's Manual, page 325, PCI
- * configuration space address format:
- * 
- *  32             24 23 16 15    11 10       8 7   2  1 0
- * ---------------------------------------------------------
- * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
- * ---------------------------------------------------------
- */
-#define SABRE_CONFIG_BASE(PBM)  \
-        ((PBM)->config_space | (1UL << 24))
-#define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG)    \
-        (((unsigned long)(BUS)   << 16) |       \
-         ((unsigned long)(DEVFN) << 8)  |       \
-         ((unsigned long)(REG)))
-
 static int hummingbird_p;
 static struct pci_bus *sabre_root_bus;
 
-static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
-                                     unsigned char bus,
-                                     unsigned int devfn,
-                                     int where)
-{
-        if (!pbm)
-                return NULL;
-        return (void *)
-                (SABRE_CONFIG_BASE(pbm) |
-                 SABRE_CONFIG_ENCODE(bus, devfn, where));
-}
-
-static int sabre_out_of_range(unsigned char devfn)
-{
-        if (hummingbird_p)
-                return 0;
-
-        return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
-                ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
-                (PCI_SLOT(devfn) > 1));
-}
-
-static int __sabre_out_of_range(struct pci_pbm_info *pbm,
-                                unsigned char bus,
-                                unsigned char devfn)
-{
-        if (hummingbird_p)
-                return 0;
-
-        return ((pbm->parent == 0) ||
-                ((pbm == &pbm->parent->pbm_A) &&
-                 (bus == pbm->pci_first_busno) &&
-                 PCI_SLOT(devfn) > 8));
-}
-
-static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
-                                int where, int size, u32 *value)
-{
-        struct pci_pbm_info *pbm = bus_dev->sysdata;
-        unsigned char bus = bus_dev->number;
-        u32 *addr;
-        u16 tmp16;
-        u8 tmp8;
-
-        switch (size) {
-        case 1:
-                *value = 0xff;
-                break;
-        case 2:
-                *value = 0xffff;
-                break;
-        case 4:
-                *value = 0xffffffff;
-                break;
-        }
-
-        addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
-        if (!addr)
-                return PCIBIOS_SUCCESSFUL;
-
-        if (__sabre_out_of_range(pbm, bus, devfn))
-                return PCIBIOS_SUCCESSFUL;
-
-        switch (size) {
-        case 1:
-                pci_config_read8((u8 *) addr, &tmp8);
-                *value = tmp8;
-                break;
-
-        case 2:
-                if (where & 0x01) {
-                        printk("pci_read_config_word: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_read16((u16 *) addr, &tmp16);
-                *value = tmp16;
-                break;
-
-        case 4:
-                if (where & 0x03) {
-                        printk("pci_read_config_dword: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_read32(addr, value);
-                break;
-        }
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
-                              int where, int size, u32 *value)
-{
-        struct pci_pbm_info *pbm = bus->sysdata;
-
-        if (bus == pbm->pci_bus && devfn == 0x00)
-                return pci_host_bridge_read_pci_cfg(bus, devfn, where,
-                                                    size, value);
-
-        if (!bus->number && sabre_out_of_range(devfn)) {
-                switch (size) {
-                case 1:
-                        *value = 0xff;
-                        break;
-                case 2:
-                        *value = 0xffff;
-                        break;
-                case 4:
-                        *value = 0xffffffff;
-                        break;
-                }
-                return PCIBIOS_SUCCESSFUL;
-        }
-
-        if (bus->number || PCI_SLOT(devfn))
-                return __sabre_read_pci_cfg(bus, devfn, where, size, value);
-
-        /* When accessing PCI config space of the PCI controller itself (bus
-         * 0, device slot 0, function 0) there are restrictions.  Each
-         * register must be accessed as it's natural size.  Thus, for example
-         * the Vendor ID must be accessed as a 16-bit quantity.
-         */
-
-        switch (size) {
-        case 1:
-                if (where < 8) {
-                        u32 tmp32;
-                        u16 tmp16;
-
-                        __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
-                        tmp16 = (u16) tmp32;
-                        if (where & 1)
-                                *value = tmp16 >> 8;
-                        else
-                                *value = tmp16 & 0xff;
-                } else
-                        return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
-                break;
-
-        case 2:
-                if (where < 8)
-                        return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
-                else {
-                        u32 tmp32;
-                        u8 tmp8;
-
-                        __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
-                        tmp8 = (u8) tmp32;
-                        *value = tmp8;
-                        __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
-                        tmp8 = (u8) tmp32;
-                        *value |= tmp8 << 8;
-                }
-                break;
-
-        case 4: {
-                u32 tmp32;
-                u16 tmp16;
-
-                sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
-                tmp16 = (u16) tmp32;
-                *value = tmp16;
-                sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
-                tmp16 = (u16) tmp32;
-                *value |= tmp16 << 16;
-                break;
-        }
-        }
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
-                                 int where, int size, u32 value)
-{
-        struct pci_pbm_info *pbm = bus_dev->sysdata;
-        unsigned char bus = bus_dev->number;
-        u32 *addr;
-
-        addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
-        if (!addr)
-                return PCIBIOS_SUCCESSFUL;
-
-        if (__sabre_out_of_range(pbm, bus, devfn))
-                return PCIBIOS_SUCCESSFUL;
-
-        switch (size) {
-        case 1:
-                pci_config_write8((u8 *) addr, value);
-                break;
-
-        case 2:
-                if (where & 0x01) {
-                        printk("pci_write_config_word: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_write16((u16 *) addr, value);
-                break;
-
-        case 4:
-                if (where & 0x03) {
-                        printk("pci_write_config_dword: misaligned reg [%x]\n",
-                               where);
-                        return PCIBIOS_SUCCESSFUL;
-                }
-                pci_config_write32(addr, value);
-                break;
-        }
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
-                               int where, int size, u32 value)
-{
-        struct pci_pbm_info *pbm = bus->sysdata;
-
-        if (bus == pbm->pci_bus && devfn == 0x00)
-                return pci_host_bridge_write_pci_cfg(bus, devfn, where,
-                                                     size, value);
-
-        if (bus->number)
-                return __sabre_write_pci_cfg(bus, devfn, where, size, value);
-
-        if (sabre_out_of_range(devfn))
-                return PCIBIOS_SUCCESSFUL;
-
-        switch (size) {
-        case 1:
-                if (where < 8) {
-                        u32 tmp32;
-                        u16 tmp16;
-
-                        __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
-                        tmp16 = (u16) tmp32;
-                        if (where & 1) {
-                                value &= 0x00ff;
-                                value |= tmp16 << 8;
-                        } else {
-                                value &= 0xff00;
-                                value |= tmp16;
-                        }
-                        tmp32 = (u32) tmp16;
-                        return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
-                } else
-                        return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
-                break;
-        case 2:
-                if (where < 8)
-                        return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
-                else {
-                        __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
-                        __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
-                }
-                break;
-        case 4:
-                sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
-                sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
-                break;
-        }
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops sabre_ops = {
-        .read =         sabre_read_pci_cfg,
-        .write =        sabre_write_pci_cfg,
-};
-
 /* SABRE error handling support. */
 static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
                                     unsigned long afsr,
@@ -1010,7 +725,8 @@ static void sabre_pbm_init(struct pci_controller_info *p, struct pci_pbm_info *p
         printk("%s: SABRE PCI Bus Module\n", pbm->name);
 
         pbm->scan_bus = sabre_scan_bus;
-        pbm->pci_ops = &sabre_ops;
+        pbm->pci_ops = &sun4u_pci_ops;
+        pbm->config_space_reg_bits = 8;
 
         pbm->index = pci_num_pbms++;