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authorDavid S. Miller <davem@sunset.davemloft.net>2007-03-01 02:35:04 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2007-04-26 04:55:06 -0400
commita2fb23af1c31ad6e0c281e56d385f803229d57fa (patch)
tree9c093cd9cc639cfaac4e2b1057f5d45eb6ab69e3 /arch/sparc64/kernel/pci_sabre.c
parentdeb66c4521e119442aa266553e8cbfc86eb71232 (diff)
[SPARC64]: Probe PCI bus using OF device tree.
Almost entirely taken from the 64-bit PowerPC PCI code. This allowed to eliminate a ton of cruft from the sparc64 PCI layer. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_sabre.c')
-rw-r--r--arch/sparc64/kernel/pci_sabre.c53
1 files changed, 8 insertions, 45 deletions
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 94bb681f2323..bbf624517508 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -710,8 +710,8 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
710 p->index); 710 p->index);
711 ret = IRQ_HANDLED; 711 ret = IRQ_HANDLED;
712 } 712 }
713 pci_read_config_word(sabre_root_bus->self, 713 pci_bus_read_config_word(sabre_root_bus, 0,
714 PCI_STATUS, &stat); 714 PCI_STATUS, &stat);
715 if (stat & (PCI_STATUS_PARITY | 715 if (stat & (PCI_STATUS_PARITY |
716 PCI_STATUS_SIG_TARGET_ABORT | 716 PCI_STATUS_SIG_TARGET_ABORT |
717 PCI_STATUS_REC_TARGET_ABORT | 717 PCI_STATUS_REC_TARGET_ABORT |
@@ -719,8 +719,8 @@ static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
719 PCI_STATUS_SIG_SYSTEM_ERROR)) { 719 PCI_STATUS_SIG_SYSTEM_ERROR)) {
720 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n", 720 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
721 p->index, stat); 721 p->index, stat);
722 pci_write_config_word(sabre_root_bus->self, 722 pci_bus_write_config_word(sabre_root_bus, 0,
723 PCI_STATUS, 0xffff); 723 PCI_STATUS, 0xffff);
724 ret = IRQ_HANDLED; 724 ret = IRQ_HANDLED;
725 } 725 }
726 return ret; 726 return ret;
@@ -887,8 +887,7 @@ static void sabre_resource_adjust(struct pci_dev *pdev,
887 887
888static void sabre_base_address_update(struct pci_dev *pdev, int resource) 888static void sabre_base_address_update(struct pci_dev *pdev, int resource)
889{ 889{
890 struct pcidev_cookie *pcp = pdev->sysdata; 890 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
891 struct pci_pbm_info *pbm = pcp->pbm;
892 struct resource *res; 891 struct resource *res;
893 unsigned long base; 892 unsigned long base;
894 u32 reg; 893 u32 reg;
@@ -978,27 +977,11 @@ static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
978 } 977 }
979} 978}
980 979
981static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
982{
983 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
984
985 if (!cookie) {
986 prom_printf("SABRE: Critical allocation failure.\n");
987 prom_halt();
988 }
989
990 /* All we care about is the PBM. */
991 cookie->pbm = pbm;
992
993 return cookie;
994}
995
996static void sabre_scan_bus(struct pci_controller_info *p) 980static void sabre_scan_bus(struct pci_controller_info *p)
997{ 981{
998 static int once; 982 static int once;
999 struct pci_bus *sabre_bus, *pbus; 983 struct pci_bus *sabre_bus, *pbus;
1000 struct pci_pbm_info *pbm; 984 struct pci_pbm_info *pbm;
1001 struct pcidev_cookie *cookie;
1002 int sabres_scanned; 985 int sabres_scanned;
1003 986
1004 /* The APB bridge speaks to the Sabre host PCI bridge 987 /* The APB bridge speaks to the Sabre host PCI bridge
@@ -1020,13 +1003,9 @@ static void sabre_scan_bus(struct pci_controller_info *p)
1020 } 1003 }
1021 once++; 1004 once++;
1022 1005
1023 cookie = alloc_bridge_cookie(&p->pbm_A); 1006 sabre_bus = pci_scan_one_pbm(&p->pbm_A);
1024 1007 if (!sabre_bus)
1025 sabre_bus = pci_scan_bus(p->pci_first_busno, 1008 return;
1026 p->pci_ops,
1027 &p->pbm_A);
1028 pci_fixup_host_bridge_self(sabre_bus);
1029 sabre_bus->self->sysdata = cookie;
1030 1009
1031 sabre_root_bus = sabre_bus; 1010 sabre_root_bus = sabre_bus;
1032 1011
@@ -1043,19 +1022,9 @@ static void sabre_scan_bus(struct pci_controller_info *p)
1043 } else 1022 } else
1044 continue; 1023 continue;
1045 1024
1046 cookie = alloc_bridge_cookie(pbm);
1047 pbus->self->sysdata = cookie;
1048
1049 sabres_scanned++; 1025 sabres_scanned++;
1050
1051 pbus->sysdata = pbm; 1026 pbus->sysdata = pbm;
1052 pbm->pci_bus = pbus; 1027 pbm->pci_bus = pbus;
1053 pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
1054 pci_record_assignments(pbm, pbus);
1055 pci_assign_unassigned(pbm, pbus);
1056 pci_fixup_irq(pbm, pbus);
1057 pci_determine_66mhz_disposition(pbm, pbus);
1058 pci_setup_busmastering(pbm, pbus);
1059 } 1028 }
1060 1029
1061 if (!sabres_scanned) { 1030 if (!sabres_scanned) {
@@ -1063,12 +1032,6 @@ static void sabre_scan_bus(struct pci_controller_info *p)
1063 pbm = &p->pbm_A; 1032 pbm = &p->pbm_A;
1064 sabre_bus->sysdata = pbm; 1033 sabre_bus->sysdata = pbm;
1065 pbm->pci_bus = sabre_bus; 1034 pbm->pci_bus = sabre_bus;
1066 pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
1067 pci_record_assignments(pbm, sabre_bus);
1068 pci_assign_unassigned(pbm, sabre_bus);
1069 pci_fixup_irq(pbm, sabre_bus);
1070 pci_determine_66mhz_disposition(pbm, sabre_bus);
1071 pci_setup_busmastering(pbm, sabre_bus);
1072 } 1035 }
1073 1036
1074 sabre_register_error_handlers(p); 1037 sabre_register_error_handlers(p);