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authorDavid S. Miller <davem@sunset.davemloft.net>2007-03-09 01:46:02 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2007-04-26 04:55:15 -0400
commit8d3aee937596d2ca6676c2c27789751445bf0bc9 (patch)
treeb22a333a9947ab94d8c35c13b4989cde53630ac9 /arch/sparc64/kernel/pci_sabre.c
parent0bae5f81b6f8130f5197e59b0e2ad6820c766b2b (diff)
[SPARC64]: Kill pci_controller->base_address_update().
Implemented but never actually used. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_sabre.c')
-rw-r--r--arch/sparc64/kernel/pci_sabre.c46
1 files changed, 0 insertions, 46 deletions
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 64cdce81d86a..f3ec7bdacdc0 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -862,51 +862,6 @@ static void sabre_register_error_handlers(struct pci_controller_info *p)
862 sabre_write(base + SABRE_PCICTRL, tmp); 862 sabre_write(base + SABRE_PCICTRL, tmp);
863} 863}
864 864
865static void sabre_base_address_update(struct pci_dev *pdev, int resource)
866{
867 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
868 struct resource *res;
869 unsigned long base;
870 u32 reg;
871 int where, size, is_64bit;
872
873 res = &pdev->resource[resource];
874 if (resource < 6) {
875 where = PCI_BASE_ADDRESS_0 + (resource * 4);
876 } else if (resource == PCI_ROM_RESOURCE) {
877 where = pdev->rom_base_reg;
878 } else {
879 /* Somebody might have asked allocation of a non-standard resource */
880 return;
881 }
882
883 is_64bit = 0;
884 if (res->flags & IORESOURCE_IO)
885 base = pbm->controller_regs + SABRE_IOSPACE;
886 else {
887 base = pbm->controller_regs + SABRE_MEMSPACE;
888 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
889 == PCI_BASE_ADDRESS_MEM_TYPE_64)
890 is_64bit = 1;
891 }
892
893 size = res->end - res->start;
894 pci_read_config_dword(pdev, where, &reg);
895 reg = ((reg & size) |
896 (((u32)(res->start - base)) & ~size));
897 if (resource == PCI_ROM_RESOURCE) {
898 reg |= PCI_ROM_ADDRESS_ENABLE;
899 res->flags |= IORESOURCE_ROM_ENABLE;
900 }
901 pci_write_config_dword(pdev, where, reg);
902
903 /* This knows that the upper 32-bits of the address
904 * must be zero. Our PCI common layer enforces this.
905 */
906 if (is_64bit)
907 pci_write_config_dword(pdev, where + 4, 0);
908}
909
910static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus) 865static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
911{ 866{
912 struct pci_dev *pdev; 867 struct pci_dev *pdev;
@@ -1099,7 +1054,6 @@ void sabre_init(struct device_node *dp, char *model_name)
1099 p->index = pci_num_controllers++; 1054 p->index = pci_num_controllers++;
1100 p->pbms_same_domain = 1; 1055 p->pbms_same_domain = 1;
1101 p->scan_bus = sabre_scan_bus; 1056 p->scan_bus = sabre_scan_bus;
1102 p->base_address_update = sabre_base_address_update;
1103 p->pci_ops = &sabre_ops; 1057 p->pci_ops = &sabre_ops;
1104 1058
1105 /* 1059 /*