diff options
author | David S. Miller <davem@sunset.davemloft.net> | 2005-10-14 00:10:08 -0400 |
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committer | David S. Miller <davem@sunset.davemloft.net> | 2005-10-14 00:10:08 -0400 |
commit | 51e8513615ed8202b22ba9a43b0c7376ea4f6868 (patch) | |
tree | 17242822a3520e2075448ac294c98adfe44a0583 /arch/sparc64/kernel/pci_sabre.c | |
parent | c931488cc4619eecfe68a2f046b5898fddc2f904 (diff) |
[SPARC64]: Consolidate common PCI IOMMU init code.
All the PCI controller drivers were doing the same thing
setting up the IOMMU software state, put it all in one spot.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_sabre.c')
-rw-r--r-- | arch/sparc64/kernel/pci_sabre.c | 39 |
1 files changed, 4 insertions, 35 deletions
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c index 0ee6bd5b9ac6..da8e1364194f 100644 --- a/arch/sparc64/kernel/pci_sabre.c +++ b/arch/sparc64/kernel/pci_sabre.c | |||
@@ -1267,13 +1267,9 @@ static void sabre_iommu_init(struct pci_controller_info *p, | |||
1267 | u32 dma_mask) | 1267 | u32 dma_mask) |
1268 | { | 1268 | { |
1269 | struct pci_iommu *iommu = p->pbm_A.iommu; | 1269 | struct pci_iommu *iommu = p->pbm_A.iommu; |
1270 | unsigned long tsbbase, i, order; | 1270 | unsigned long i; |
1271 | u64 control; | 1271 | u64 control; |
1272 | 1272 | ||
1273 | /* Setup initial software IOMMU state. */ | ||
1274 | spin_lock_init(&iommu->lock); | ||
1275 | iommu->ctx_lowest_free = 1; | ||
1276 | |||
1277 | /* Register addresses. */ | 1273 | /* Register addresses. */ |
1278 | iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL; | 1274 | iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL; |
1279 | iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE; | 1275 | iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE; |
@@ -1295,26 +1291,10 @@ static void sabre_iommu_init(struct pci_controller_info *p, | |||
1295 | /* Leave diag mode enabled for full-flushing done | 1291 | /* Leave diag mode enabled for full-flushing done |
1296 | * in pci_iommu.c | 1292 | * in pci_iommu.c |
1297 | */ | 1293 | */ |
1294 | pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask); | ||
1298 | 1295 | ||
1299 | iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0); | 1296 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE, |
1300 | if (!iommu->dummy_page) { | 1297 | __pa(iommu->page_table)); |
1301 | prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n"); | ||
1302 | prom_halt(); | ||
1303 | } | ||
1304 | memset((void *)iommu->dummy_page, 0, PAGE_SIZE); | ||
1305 | iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); | ||
1306 | |||
1307 | tsbbase = __get_free_pages(GFP_KERNEL, order = get_order(tsbsize * 1024 * 8)); | ||
1308 | if (!tsbbase) { | ||
1309 | prom_printf("SABRE_IOMMU: Error, gfp(tsb) failed.\n"); | ||
1310 | prom_halt(); | ||
1311 | } | ||
1312 | iommu->page_table = (iopte_t *)tsbbase; | ||
1313 | iommu->page_table_map_base = dvma_offset; | ||
1314 | iommu->dma_addr_mask = dma_mask; | ||
1315 | pci_iommu_table_init(iommu, PAGE_SIZE << order); | ||
1316 | |||
1317 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE, __pa(tsbbase)); | ||
1318 | 1298 | ||
1319 | control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL); | 1299 | control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL); |
1320 | control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ); | 1300 | control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ); |
@@ -1322,11 +1302,9 @@ static void sabre_iommu_init(struct pci_controller_info *p, | |||
1322 | switch(tsbsize) { | 1302 | switch(tsbsize) { |
1323 | case 64: | 1303 | case 64: |
1324 | control |= SABRE_IOMMU_TSBSZ_64K; | 1304 | control |= SABRE_IOMMU_TSBSZ_64K; |
1325 | iommu->page_table_sz_bits = 16; | ||
1326 | break; | 1305 | break; |
1327 | case 128: | 1306 | case 128: |
1328 | control |= SABRE_IOMMU_TSBSZ_128K; | 1307 | control |= SABRE_IOMMU_TSBSZ_128K; |
1329 | iommu->page_table_sz_bits = 17; | ||
1330 | break; | 1308 | break; |
1331 | default: | 1309 | default: |
1332 | prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize); | 1310 | prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize); |
@@ -1334,15 +1312,6 @@ static void sabre_iommu_init(struct pci_controller_info *p, | |||
1334 | break; | 1312 | break; |
1335 | } | 1313 | } |
1336 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control); | 1314 | sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control); |
1337 | |||
1338 | /* We start with no consistent mappings. */ | ||
1339 | iommu->lowest_consistent_map = | ||
1340 | 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS); | ||
1341 | |||
1342 | for (i = 0; i < PBM_NCLUSTERS; i++) { | ||
1343 | iommu->alloc_info[i].flush = 0; | ||
1344 | iommu->alloc_info[i].next = 0; | ||
1345 | } | ||
1346 | } | 1315 | } |
1347 | 1316 | ||
1348 | static void pbm_register_toplevel_resources(struct pci_controller_info *p, | 1317 | static void pbm_register_toplevel_resources(struct pci_controller_info *p, |