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authorDavid S. Miller <davem@sunset.davemloft.net>2007-03-09 01:46:02 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2007-04-26 04:55:15 -0400
commit8d3aee937596d2ca6676c2c27789751445bf0bc9 (patch)
treeb22a333a9947ab94d8c35c13b4989cde53630ac9 /arch/sparc64/kernel/pci_psycho.c
parent0bae5f81b6f8130f5197e59b0e2ad6820c766b2b (diff)
[SPARC64]: Kill pci_controller->base_address_update().
Implemented but never actually used. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_psycho.c')
-rw-r--r--arch/sparc64/kernel/pci_psycho.c45
1 files changed, 0 insertions, 45 deletions
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index c3f212725b04..64bd3579f1ca 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -894,50 +894,6 @@ static void psycho_register_error_handlers(struct pci_controller_info *p)
894} 894}
895 895
896/* PSYCHO boot time probing and initialization. */ 896/* PSYCHO boot time probing and initialization. */
897static void psycho_base_address_update(struct pci_dev *pdev, int resource)
898{
899 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
900 struct resource *res, *root;
901 u32 reg;
902 int where, size, is_64bit;
903
904 res = &pdev->resource[resource];
905 if (resource < 6) {
906 where = PCI_BASE_ADDRESS_0 + (resource * 4);
907 } else if (resource == PCI_ROM_RESOURCE) {
908 where = pdev->rom_base_reg;
909 } else {
910 /* Somebody might have asked allocation of a non-standard resource */
911 return;
912 }
913
914 is_64bit = 0;
915 if (res->flags & IORESOURCE_IO)
916 root = &pbm->io_space;
917 else {
918 root = &pbm->mem_space;
919 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
920 == PCI_BASE_ADDRESS_MEM_TYPE_64)
921 is_64bit = 1;
922 }
923
924 size = res->end - res->start;
925 pci_read_config_dword(pdev, where, &reg);
926 reg = ((reg & size) |
927 (((u32)(res->start - root->start)) & ~size));
928 if (resource == PCI_ROM_RESOURCE) {
929 reg |= PCI_ROM_ADDRESS_ENABLE;
930 res->flags |= IORESOURCE_ROM_ENABLE;
931 }
932 pci_write_config_dword(pdev, where, reg);
933
934 /* This knows that the upper 32-bits of the address
935 * must be zero. Our PCI common layer enforces this.
936 */
937 if (is_64bit)
938 pci_write_config_dword(pdev, where + 4, 0);
939}
940
941static void pbm_config_busmastering(struct pci_pbm_info *pbm) 897static void pbm_config_busmastering(struct pci_pbm_info *pbm)
942{ 898{
943 u8 *addr; 899 u8 *addr;
@@ -1209,7 +1165,6 @@ void psycho_init(struct device_node *dp, char *model_name)
1209 p->index = pci_num_controllers++; 1165 p->index = pci_num_controllers++;
1210 p->pbms_same_domain = 0; 1166 p->pbms_same_domain = 0;
1211 p->scan_bus = psycho_scan_bus; 1167 p->scan_bus = psycho_scan_bus;
1212 p->base_address_update = psycho_base_address_update;
1213 p->pci_ops = &psycho_ops; 1168 p->pci_ops = &psycho_ops;
1214 1169
1215 prop = of_find_property(dp, "reg", NULL); 1170 prop = of_find_property(dp, "reg", NULL);