[SPARC64]: SUN4U PCI-E controller support.

Some minor refactoring in the generic code was necessary for
this:

1) This controller requires 8-byte access to the interrupt map
   and clear register.  They are 64-bits on all the other
   SBUS and PCI controllers anyways, so this was easy to cure.

2) The IMAP register has a different layout and some bits that we
   need to preserve, so use a read/modify/write when making
   changes to the IMAP register in generic code.

3) Flushing the entire IOMMU TLB is best done with a single write
   to a register on this PCI controller, add a iommu->iommu_flushinv
   for this.

Still lacks MSI support, that will come later.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 13 insertions, 9 deletions

diff --git a/arch/sparc64/kernel/pci_iommu.c b/arch/sparc64/kernel/pci_iommu.c
index 66712772f494..9e405cbbcb0d 100644
--- a/arch/sparc64/kernel/pci_iommu.c
+++ b/arch/sparc64/kernel/pci_iommu.c
@@ -37,17 +37,21 @@
 /* Must be invoked under the IOMMU lock. */
 static void __iommu_flushall(struct iommu *iommu)
 {
-        unsigned long tag;
-        int entry;
+        if (iommu->iommu_flushinv) {
+                pci_iommu_write(iommu->iommu_flushinv, ~(u64)0);
+        } else {
+                unsigned long tag;
+                int entry;
 
-        tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
-        for (entry = 0; entry < 16; entry++) {
-                pci_iommu_write(tag, 0);
-                tag += 8;
-        }
+                tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
+                for (entry = 0; entry < 16; entry++) {
+                        pci_iommu_write(tag, 0);
+                        tag += 8;
+                }
 
-        /* Ensure completion of previous PIO writes. */
-        (void) pci_iommu_read(iommu->write_complete_reg);
+                /* Ensure completion of previous PIO writes. */
+                (void) pci_iommu_read(iommu->write_complete_reg);
+        }
 }
 
 #define IOPTE_CONSISTENT(CTX) \