[SPARC64]: SUN4U PCI-E controller support.

Some minor refactoring in the generic code was necessary for
this:

1) This controller requires 8-byte access to the interrupt map
   and clear register.  They are 64-bits on all the other
   SBUS and PCI controllers anyways, so this was easy to cure.

2) The IMAP register has a different layout and some bits that we
   need to preserve, so use a read/modify/write when making
   changes to the IMAP register in generic code.

3) Flushing the entire IOMMU TLB is best done with a single write
   to a register on this PCI controller, add a iommu->iommu_flushinv
   for this.

Still lacks MSI support, that will come later.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 9 insertions, 0 deletions

diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index 9a549547cb2b..a72a3c312d33 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -190,6 +190,7 @@ extern void schizo_init(struct device_node *, const char *);
 extern void schizo_plus_init(struct device_node *, const char *);
 extern void tomatillo_init(struct device_node *, const char *);
 extern void sun4v_pci_init(struct device_node *, const char *);
+extern void fire_pci_init(struct device_node *, const char *);
 
 static struct {
         char *model_name;
@@ -207,6 +208,7 @@ static struct {
         { "SUNW,tomatillo", tomatillo_init },
         { "pci108e,a801", tomatillo_init },
         { "SUNW,sun4v-pci", sun4v_pci_init },
+        { "pciex108e,80f0", fire_pci_init },
 };
 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
                                   sizeof(pci_controller_table[0]))
@@ -436,6 +438,13 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
         printk("    class: 0x%x device name: %s\n",
                dev->class, pci_name(dev));
 
+        /* I have seen IDE devices which will not respond to
+         * the bmdma simplex check reads if bus mastering is
+         * disabled.
+         */
+        if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
+                pci_set_master(dev);
+
         dev->current_state = 4;         /* unknown power state */
         dev->error_state = pci_channel_io_normal;