[SPARC64]: Add CONFIG_DEBUG_PAGEALLOC support.

The trick is that we do the kernel linear mapping TLB miss starting
with an instruction sequence like this:

	ba,pt		%xcc, kvmap_load
	 xor		%g2, %g4, %g5

succeeded by an instruction sequence which performs a full page table
walk starting at swapper_pg_dir.

We first take over the trap table from the firmware.  Then, using this
constant PTE generation for the linear mapping area above, we build
the kernel page tables for the linear mapping.

After this is setup, we patch that branch above into a "nop", which
will cause TLB misses to fall through to the full page table walk.

With this, the page unmapping for CONFIG_DEBUG_PAGEALLOC is trivial.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 32 insertions, 1 deletions

diff --git a/arch/sparc64/kernel/ktlb.S b/arch/sparc64/kernel/ktlb.S
index a591bc0ebc7b..7796b37f478c 100644
--- a/arch/sparc64/kernel/ktlb.S
+++ b/arch/sparc64/kernel/ktlb.S
@@ -132,9 +132,40 @@ kvmap_do_obp:
  */
         .align          32
 kvmap:
-        brlz,pt         %g4, kvmap_load
+        brgez,pn        %g4, kvmap_nonlinear
+         nop
+
+#ifdef CONFIG_DEBUG_PAGEALLOC
+        .globl          kvmap_linear_patch
+kvmap_linear_patch:
+#endif
+        ba,pt           %xcc, kvmap_load
          xor            %g2, %g4, %g5
 
+#ifdef CONFIG_DEBUG_PAGEALLOC
+        sethi           %hi(swapper_pg_dir), %g5
+        or              %g5, %lo(swapper_pg_dir), %g5
+        sllx            %g4, 64 - (PGDIR_SHIFT + PGDIR_BITS), %g6
+        srlx            %g6, 64 - PAGE_SHIFT, %g6
+        andn            %g6, 0x3, %g6
+        lduw            [%g5 + %g6], %g5
+        brz,pn          %g5, longpath
+         sllx           %g4, 64 - (PMD_SHIFT + PMD_BITS), %g6
+        srlx            %g6, 64 - PAGE_SHIFT, %g6
+        sllx            %g5, 11, %g5
+        andn            %g6, 0x3, %g6
+        lduwa           [%g5 + %g6] ASI_PHYS_USE_EC, %g5
+        brz,pn          %g5, longpath
+         sllx           %g4, 64 - PMD_SHIFT, %g6
+        srlx            %g6, 64 - PAGE_SHIFT, %g6
+        sllx            %g5, 11, %g5
+        andn            %g6, 0x7, %g6
+        ldxa            [%g5 + %g6] ASI_PHYS_USE_EC, %g5
+        brz,pn          %g5, longpath
+         nop
+        ba,a,pt         %xcc, kvmap_load
+#endif
+
 kvmap_nonlinear:
         sethi           %hi(MODULES_VADDR), %g5
         cmp             %g4, %g5