[SPARC64]: Deal with PTE layout differences in SUN4V.

Yes, you heard it right, they changed the PTE layout for
SUN4V.  Ho hum...

This is the simple and inefficient way to support this.
It'll get optimized, don't worry.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/sparc64/kernel/itlb_miss.S b/arch/sparc64/kernel/itlb_miss.S
index 97facce27aad..730caa4a1506 100644
--- a/arch/sparc64/kernel/itlb_miss.S
+++ b/arch/sparc64/kernel/itlb_miss.S
@@ -6,9 +6,10 @@
          nop                                    ! Delay slot (fill me)
         TSB_LOAD_QUAD(%g1, %g4)                 ! Load TSB entry
         cmp     %g4, %g6                        ! Compare TAG
-        sethi   %hi(_PAGE_EXEC), %g4            ! Setup exec check
+        sethi   %hi(PAGE_EXEC), %g4             ! Setup exec check
 
 /* ITLB ** ICACHE line 2: TSB compare and TLB load      */
+        ldx     [%g4 + %lo(PAGE_EXEC)], %g4
         bne,pn  %xcc, tsb_miss_itlb             ! Miss
          mov    FAULT_CODE_ITLB, %g3
         andcc   %g5, %g4, %g0                   ! Executable?
@@ -16,7 +17,6 @@
          nop                                    ! Delay slot, fill me
         stxa    %g5, [%g0] ASI_ITLB_DATA_IN     ! Load TLB
         retry                                   ! Trap done
-        nop
 
 /* ITLB ** ICACHE line 3:                               */
         nop