[SPARC64]: Patch up mmu context register writes for sun4v.

sun4v uses ASI_MMU instead of ASI_DMMU

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 26 insertions, 7 deletions

diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index f04f7391f236..a304845f8c56 100644
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -303,12 +303,24 @@ jump_to_sun4u_init:
 
 sun4u_init:
         /* Set ctx 0 */
-        mov     PRIMARY_CONTEXT, %g7
-        stxa    %g0, [%g7] ASI_DMMU
-        membar  #Sync
+        mov             PRIMARY_CONTEXT, %g7
+
+661:    stxa            %g0, [%g7] ASI_DMMU
+        .section        .sun4v_1insn_patch, "ax"
+        .word           661b
+        stxa            %g0, [%g7] ASI_MMU
+        .previous
+
+        membar          #Sync
+
+        mov             SECONDARY_CONTEXT, %g7
+
+661:    stxa            %g0, [%g7] ASI_DMMU
+        .section        .sun4v_1insn_patch, "ax"
+        .word           661b
+        stxa            %g0, [%g7] ASI_MMU
+        .previous
 
-        mov     SECONDARY_CONTEXT, %g7
-        stxa    %g0, [%g7] ASI_DMMU
         membar  #Sync
 
         BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup)
@@ -436,8 +448,15 @@ setup_trap_table:
         /* Start using proper page size encodings in ctx register.  */
         sethi   %hi(sparc64_kern_pri_context), %g3
         ldx     [%g3 + %lo(sparc64_kern_pri_context)], %g2
-        mov     PRIMARY_CONTEXT, %g1
-        stxa    %g2, [%g1] ASI_DMMU
+
+        mov             PRIMARY_CONTEXT, %g1
+
+661:    stxa            %g2, [%g1] ASI_DMMU
+        .section        .sun4v_1insn_patch, "ax"
+        .word           661b
+        stxa            %g2, [%g1] ASI_MMU
+        .previous
+
         membar  #Sync
 
         /* Kill PROM timer */