sparc64: Run the kernel always in the TSO memory model.

The fact of the matter is, all UltraSPARC-III and later chips only
implement TSO.  They don't implement PSO and RMO memory models at all.

Only the Ultra-I and Ultra-II family chips implement RMO and they are
only helped marginally by using this setting when executing kernel
code.

The big plus to doing this is that we can eliminate all of the non-Sync
memory barriers in the kernel except for the ones used in the optimized
memcpy/memset code (these use block load and store operations which
have their own memory ordering rules).

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 3 insertions, 3 deletions

diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S
index 29ce489bc188..786b185e6e3f 100644
--- a/arch/sparc64/kernel/etrap.S
+++ b/arch/sparc64/kernel/etrap.S
@@ -16,9 +16,9 @@
 #include <asm/mmu.h>
 
 #define         TASK_REGOFF             (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
-#define         ETRAP_PSTATE1           (PSTATE_RMO | PSTATE_PRIV)
+#define         ETRAP_PSTATE1           (PSTATE_TSO | PSTATE_PRIV)
 #define         ETRAP_PSTATE2           \
-                (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
+                (PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
 
 /*
  * On entry, %g7 is return address - 0x4.
@@ -130,7 +130,7 @@ etrap_save:	save	%g2, -STACK_BIAS, %sp
                 stx     %g6, [%sp + PTREGS_OFF + PT_V9_G6]
                 stx     %g7, [%sp + PTREGS_OFF + PT_V9_G7]
                 or      %l7, %l0, %l7
-                sethi   %hi(TSTATE_RMO | TSTATE_PEF), %l0
+                sethi   %hi(TSTATE_TSO | TSTATE_PEF), %l0
                 or      %l7, %l0, %l7
                 wrpr    %l2, %tnpc
                 wrpr    %l7, (TSTATE_PRIV | TSTATE_IE), %tstate