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authorDavid S. Miller <davem@davemloft.net>2008-04-28 03:47:20 -0400
committerDavid S. Miller <davem@davemloft.net>2008-04-28 03:47:20 -0400
commit6eda3a75928a3dc1072dfffd228ab818869d83ad (patch)
tree56e44907f23134273fe383424c69df4d62c6544c /arch/sparc64/kernel/entry.S
parent194f1a68b93e959ede6ec363db4714e630bdbb6a (diff)
sparc64: Split entry.S up into seperate files.
entry.S was a hodge-podge of several totally unrelated sets of assembler routines, ranging from FPU trap handlers to hypervisor call functions. Split it up into topic-sized pieces. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/entry.S')
-rw-r--r--arch/sparc64/kernel/entry.S2575
1 files changed, 0 insertions, 2575 deletions
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
deleted file mode 100644
index fd06e937ae1e..000000000000
--- a/arch/sparc64/kernel/entry.S
+++ /dev/null
@@ -1,2575 +0,0 @@
1/* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10#include <linux/errno.h>
11
12#include <asm/head.h>
13#include <asm/asi.h>
14#include <asm/smp.h>
15#include <asm/ptrace.h>
16#include <asm/page.h>
17#include <asm/signal.h>
18#include <asm/pgtable.h>
19#include <asm/processor.h>
20#include <asm/visasm.h>
21#include <asm/estate.h>
22#include <asm/auxio.h>
23#include <asm/sfafsr.h>
24#include <asm/pil.h>
25#include <asm/unistd.h>
26
27#define curptr g6
28
29 .text
30 .align 32
31
32 /* This is trivial with the new code... */
33 .globl do_fpdis
34do_fpdis:
35 sethi %hi(TSTATE_PEF), %g4
36 rdpr %tstate, %g5
37 andcc %g5, %g4, %g0
38 be,pt %xcc, 1f
39 nop
40 rd %fprs, %g5
41 andcc %g5, FPRS_FEF, %g0
42 be,pt %xcc, 1f
43 nop
44
45 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
46 sethi %hi(109f), %g7
47 ba,pt %xcc, etrap
48109: or %g7, %lo(109b), %g7
49 add %g0, %g0, %g0
50 ba,a,pt %xcc, rtrap
51
521: TRAP_LOAD_THREAD_REG(%g6, %g1)
53 ldub [%g6 + TI_FPSAVED], %g5
54 wr %g0, FPRS_FEF, %fprs
55 andcc %g5, FPRS_FEF, %g0
56 be,a,pt %icc, 1f
57 clr %g7
58 ldx [%g6 + TI_GSR], %g7
591: andcc %g5, FPRS_DL, %g0
60 bne,pn %icc, 2f
61 fzero %f0
62 andcc %g5, FPRS_DU, %g0
63 bne,pn %icc, 1f
64 fzero %f2
65 faddd %f0, %f2, %f4
66 fmuld %f0, %f2, %f6
67 faddd %f0, %f2, %f8
68 fmuld %f0, %f2, %f10
69 faddd %f0, %f2, %f12
70 fmuld %f0, %f2, %f14
71 faddd %f0, %f2, %f16
72 fmuld %f0, %f2, %f18
73 faddd %f0, %f2, %f20
74 fmuld %f0, %f2, %f22
75 faddd %f0, %f2, %f24
76 fmuld %f0, %f2, %f26
77 faddd %f0, %f2, %f28
78 fmuld %f0, %f2, %f30
79 faddd %f0, %f2, %f32
80 fmuld %f0, %f2, %f34
81 faddd %f0, %f2, %f36
82 fmuld %f0, %f2, %f38
83 faddd %f0, %f2, %f40
84 fmuld %f0, %f2, %f42
85 faddd %f0, %f2, %f44
86 fmuld %f0, %f2, %f46
87 faddd %f0, %f2, %f48
88 fmuld %f0, %f2, %f50
89 faddd %f0, %f2, %f52
90 fmuld %f0, %f2, %f54
91 faddd %f0, %f2, %f56
92 fmuld %f0, %f2, %f58
93 b,pt %xcc, fpdis_exit2
94 faddd %f0, %f2, %f60
951: mov SECONDARY_CONTEXT, %g3
96 add %g6, TI_FPREGS + 0x80, %g1
97 faddd %f0, %f2, %f4
98 fmuld %f0, %f2, %f6
99
100661: ldxa [%g3] ASI_DMMU, %g5
101 .section .sun4v_1insn_patch, "ax"
102 .word 661b
103 ldxa [%g3] ASI_MMU, %g5
104 .previous
105
106 sethi %hi(sparc64_kern_sec_context), %g2
107 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
108
109661: stxa %g2, [%g3] ASI_DMMU
110 .section .sun4v_1insn_patch, "ax"
111 .word 661b
112 stxa %g2, [%g3] ASI_MMU
113 .previous
114
115 membar #Sync
116 add %g6, TI_FPREGS + 0xc0, %g2
117 faddd %f0, %f2, %f8
118 fmuld %f0, %f2, %f10
119 membar #Sync
120 ldda [%g1] ASI_BLK_S, %f32
121 ldda [%g2] ASI_BLK_S, %f48
122 membar #Sync
123 faddd %f0, %f2, %f12
124 fmuld %f0, %f2, %f14
125 faddd %f0, %f2, %f16
126 fmuld %f0, %f2, %f18
127 faddd %f0, %f2, %f20
128 fmuld %f0, %f2, %f22
129 faddd %f0, %f2, %f24
130 fmuld %f0, %f2, %f26
131 faddd %f0, %f2, %f28
132 fmuld %f0, %f2, %f30
133 b,pt %xcc, fpdis_exit
134 nop
1352: andcc %g5, FPRS_DU, %g0
136 bne,pt %icc, 3f
137 fzero %f32
138 mov SECONDARY_CONTEXT, %g3
139 fzero %f34
140
141661: ldxa [%g3] ASI_DMMU, %g5
142 .section .sun4v_1insn_patch, "ax"
143 .word 661b
144 ldxa [%g3] ASI_MMU, %g5
145 .previous
146
147 add %g6, TI_FPREGS, %g1
148 sethi %hi(sparc64_kern_sec_context), %g2
149 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
150
151661: stxa %g2, [%g3] ASI_DMMU
152 .section .sun4v_1insn_patch, "ax"
153 .word 661b
154 stxa %g2, [%g3] ASI_MMU
155 .previous
156
157 membar #Sync
158 add %g6, TI_FPREGS + 0x40, %g2
159 faddd %f32, %f34, %f36
160 fmuld %f32, %f34, %f38
161 membar #Sync
162 ldda [%g1] ASI_BLK_S, %f0
163 ldda [%g2] ASI_BLK_S, %f16
164 membar #Sync
165 faddd %f32, %f34, %f40
166 fmuld %f32, %f34, %f42
167 faddd %f32, %f34, %f44
168 fmuld %f32, %f34, %f46
169 faddd %f32, %f34, %f48
170 fmuld %f32, %f34, %f50
171 faddd %f32, %f34, %f52
172 fmuld %f32, %f34, %f54
173 faddd %f32, %f34, %f56
174 fmuld %f32, %f34, %f58
175 faddd %f32, %f34, %f60
176 fmuld %f32, %f34, %f62
177 ba,pt %xcc, fpdis_exit
178 nop
1793: mov SECONDARY_CONTEXT, %g3
180 add %g6, TI_FPREGS, %g1
181
182661: ldxa [%g3] ASI_DMMU, %g5
183 .section .sun4v_1insn_patch, "ax"
184 .word 661b
185 ldxa [%g3] ASI_MMU, %g5
186 .previous
187
188 sethi %hi(sparc64_kern_sec_context), %g2
189 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
190
191661: stxa %g2, [%g3] ASI_DMMU
192 .section .sun4v_1insn_patch, "ax"
193 .word 661b
194 stxa %g2, [%g3] ASI_MMU
195 .previous
196
197 membar #Sync
198 mov 0x40, %g2
199 membar #Sync
200 ldda [%g1] ASI_BLK_S, %f0
201 ldda [%g1 + %g2] ASI_BLK_S, %f16
202 add %g1, 0x80, %g1
203 ldda [%g1] ASI_BLK_S, %f32
204 ldda [%g1 + %g2] ASI_BLK_S, %f48
205 membar #Sync
206fpdis_exit:
207
208661: stxa %g5, [%g3] ASI_DMMU
209 .section .sun4v_1insn_patch, "ax"
210 .word 661b
211 stxa %g5, [%g3] ASI_MMU
212 .previous
213
214 membar #Sync
215fpdis_exit2:
216 wr %g7, 0, %gsr
217 ldx [%g6 + TI_XFSR], %fsr
218 rdpr %tstate, %g3
219 or %g3, %g4, %g3 ! anal...
220 wrpr %g3, %tstate
221 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
222 retry
223
224 .align 32
225fp_other_bounce:
226 call do_fpother
227 add %sp, PTREGS_OFF, %o0
228 ba,pt %xcc, rtrap
229 nop
230
231 .globl do_fpother_check_fitos
232 .align 32
233do_fpother_check_fitos:
234 TRAP_LOAD_THREAD_REG(%g6, %g1)
235 sethi %hi(fp_other_bounce - 4), %g7
236 or %g7, %lo(fp_other_bounce - 4), %g7
237
238 /* NOTE: Need to preserve %g7 until we fully commit
239 * to the fitos fixup.
240 */
241 stx %fsr, [%g6 + TI_XFSR]
242 rdpr %tstate, %g3
243 andcc %g3, TSTATE_PRIV, %g0
244 bne,pn %xcc, do_fptrap_after_fsr
245 nop
246 ldx [%g6 + TI_XFSR], %g3
247 srlx %g3, 14, %g1
248 and %g1, 7, %g1
249 cmp %g1, 2 ! Unfinished FP-OP
250 bne,pn %xcc, do_fptrap_after_fsr
251 sethi %hi(1 << 23), %g1 ! Inexact
252 andcc %g3, %g1, %g0
253 bne,pn %xcc, do_fptrap_after_fsr
254 rdpr %tpc, %g1
255 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
256#define FITOS_MASK 0xc1f83fe0
257#define FITOS_COMPARE 0x81a01880
258 sethi %hi(FITOS_MASK), %g1
259 or %g1, %lo(FITOS_MASK), %g1
260 and %g3, %g1, %g1
261 sethi %hi(FITOS_COMPARE), %g2
262 or %g2, %lo(FITOS_COMPARE), %g2
263 cmp %g1, %g2
264 bne,pn %xcc, do_fptrap_after_fsr
265 nop
266 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
267 sethi %hi(fitos_table_1), %g1
268 and %g3, 0x1f, %g2
269 or %g1, %lo(fitos_table_1), %g1
270 sllx %g2, 2, %g2
271 jmpl %g1 + %g2, %g0
272 ba,pt %xcc, fitos_emul_continue
273
274fitos_table_1:
275 fitod %f0, %f62
276 fitod %f1, %f62
277 fitod %f2, %f62
278 fitod %f3, %f62
279 fitod %f4, %f62
280 fitod %f5, %f62
281 fitod %f6, %f62
282 fitod %f7, %f62
283 fitod %f8, %f62
284 fitod %f9, %f62
285 fitod %f10, %f62
286 fitod %f11, %f62
287 fitod %f12, %f62
288 fitod %f13, %f62
289 fitod %f14, %f62
290 fitod %f15, %f62
291 fitod %f16, %f62
292 fitod %f17, %f62
293 fitod %f18, %f62
294 fitod %f19, %f62
295 fitod %f20, %f62
296 fitod %f21, %f62
297 fitod %f22, %f62
298 fitod %f23, %f62
299 fitod %f24, %f62
300 fitod %f25, %f62
301 fitod %f26, %f62
302 fitod %f27, %f62
303 fitod %f28, %f62
304 fitod %f29, %f62
305 fitod %f30, %f62
306 fitod %f31, %f62
307
308fitos_emul_continue:
309 sethi %hi(fitos_table_2), %g1
310 srl %g3, 25, %g2
311 or %g1, %lo(fitos_table_2), %g1
312 and %g2, 0x1f, %g2
313 sllx %g2, 2, %g2
314 jmpl %g1 + %g2, %g0
315 ba,pt %xcc, fitos_emul_fini
316
317fitos_table_2:
318 fdtos %f62, %f0
319 fdtos %f62, %f1
320 fdtos %f62, %f2
321 fdtos %f62, %f3
322 fdtos %f62, %f4
323 fdtos %f62, %f5
324 fdtos %f62, %f6
325 fdtos %f62, %f7
326 fdtos %f62, %f8
327 fdtos %f62, %f9
328 fdtos %f62, %f10
329 fdtos %f62, %f11
330 fdtos %f62, %f12
331 fdtos %f62, %f13
332 fdtos %f62, %f14
333 fdtos %f62, %f15
334 fdtos %f62, %f16
335 fdtos %f62, %f17
336 fdtos %f62, %f18
337 fdtos %f62, %f19
338 fdtos %f62, %f20
339 fdtos %f62, %f21
340 fdtos %f62, %f22
341 fdtos %f62, %f23
342 fdtos %f62, %f24
343 fdtos %f62, %f25
344 fdtos %f62, %f26
345 fdtos %f62, %f27
346 fdtos %f62, %f28
347 fdtos %f62, %f29
348 fdtos %f62, %f30
349 fdtos %f62, %f31
350
351fitos_emul_fini:
352 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
353 done
354
355 .globl do_fptrap
356 .align 32
357do_fptrap:
358 TRAP_LOAD_THREAD_REG(%g6, %g1)
359 stx %fsr, [%g6 + TI_XFSR]
360do_fptrap_after_fsr:
361 ldub [%g6 + TI_FPSAVED], %g3
362 rd %fprs, %g1
363 or %g3, %g1, %g3
364 stb %g3, [%g6 + TI_FPSAVED]
365 rd %gsr, %g3
366 stx %g3, [%g6 + TI_GSR]
367 mov SECONDARY_CONTEXT, %g3
368
369661: ldxa [%g3] ASI_DMMU, %g5
370 .section .sun4v_1insn_patch, "ax"
371 .word 661b
372 ldxa [%g3] ASI_MMU, %g5
373 .previous
374
375 sethi %hi(sparc64_kern_sec_context), %g2
376 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
377
378661: stxa %g2, [%g3] ASI_DMMU
379 .section .sun4v_1insn_patch, "ax"
380 .word 661b
381 stxa %g2, [%g3] ASI_MMU
382 .previous
383
384 membar #Sync
385 add %g6, TI_FPREGS, %g2
386 andcc %g1, FPRS_DL, %g0
387 be,pn %icc, 4f
388 mov 0x40, %g3
389 stda %f0, [%g2] ASI_BLK_S
390 stda %f16, [%g2 + %g3] ASI_BLK_S
391 andcc %g1, FPRS_DU, %g0
392 be,pn %icc, 5f
3934: add %g2, 128, %g2
394 stda %f32, [%g2] ASI_BLK_S
395 stda %f48, [%g2 + %g3] ASI_BLK_S
3965: mov SECONDARY_CONTEXT, %g1
397 membar #Sync
398
399661: stxa %g5, [%g1] ASI_DMMU
400 .section .sun4v_1insn_patch, "ax"
401 .word 661b
402 stxa %g5, [%g1] ASI_MMU
403 .previous
404
405 membar #Sync
406 ba,pt %xcc, etrap
407 wr %g0, 0, %fprs
408
409 /* The registers for cross calls will be:
410 *
411 * DATA 0: [low 32-bits] Address of function to call, jmp to this
412 * [high 32-bits] MMU Context Argument 0, place in %g5
413 * DATA 1: Address Argument 1, place in %g1
414 * DATA 2: Address Argument 2, place in %g7
415 *
416 * With this method we can do most of the cross-call tlb/cache
417 * flushing very quickly.
418 */
419 .text
420 .align 32
421 .globl do_ivec
422do_ivec:
423 mov 0x40, %g3
424 ldxa [%g3 + %g0] ASI_INTR_R, %g3
425 sethi %hi(KERNBASE), %g4
426 cmp %g3, %g4
427 bgeu,pn %xcc, do_ivec_xcall
428 srlx %g3, 32, %g5
429 stxa %g0, [%g0] ASI_INTR_RECEIVE
430 membar #Sync
431
432 sethi %hi(ivector_table_pa), %g2
433 ldx [%g2 + %lo(ivector_table_pa)], %g2
434 sllx %g3, 4, %g3
435 add %g2, %g3, %g3
436
437 TRAP_LOAD_IRQ_WORK_PA(%g6, %g1)
438
439 ldx [%g6], %g5
440 stxa %g5, [%g3] ASI_PHYS_USE_EC
441 stx %g3, [%g6]
442 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
443 retry
444do_ivec_xcall:
445 mov 0x50, %g1
446 ldxa [%g1 + %g0] ASI_INTR_R, %g1
447 srl %g3, 0, %g3
448
449 mov 0x60, %g7
450 ldxa [%g7 + %g0] ASI_INTR_R, %g7
451 stxa %g0, [%g0] ASI_INTR_RECEIVE
452 membar #Sync
453 ba,pt %xcc, 1f
454 nop
455
456 .align 32
4571: jmpl %g3, %g0
458 nop
459
460 .globl getcc, setcc
461getcc:
462 ldx [%o0 + PT_V9_TSTATE], %o1
463 srlx %o1, 32, %o1
464 and %o1, 0xf, %o1
465 retl
466 stx %o1, [%o0 + PT_V9_G1]
467setcc:
468 ldx [%o0 + PT_V9_TSTATE], %o1
469 ldx [%o0 + PT_V9_G1], %o2
470 or %g0, %ulo(TSTATE_ICC), %o3
471 sllx %o3, 32, %o3
472 andn %o1, %o3, %o1
473 sllx %o2, 32, %o2
474 and %o2, %o3, %o2
475 or %o1, %o2, %o1
476 retl
477 stx %o1, [%o0 + PT_V9_TSTATE]
478
479 .globl utrap_trap
480utrap_trap: /* %g3=handler,%g4=level */
481 TRAP_LOAD_THREAD_REG(%g6, %g1)
482 ldx [%g6 + TI_UTRAPS], %g1
483 brnz,pt %g1, invoke_utrap
484 nop
485
486 ba,pt %xcc, etrap
487 rd %pc, %g7
488 mov %l4, %o1
489 call bad_trap
490 add %sp, PTREGS_OFF, %o0
491 ba,pt %xcc, rtrap
492 nop
493
494invoke_utrap:
495 sllx %g3, 3, %g3
496 ldx [%g1 + %g3], %g1
497 save %sp, -128, %sp
498 rdpr %tstate, %l6
499 rdpr %cwp, %l7
500 andn %l6, TSTATE_CWP, %l6
501 wrpr %l6, %l7, %tstate
502 rdpr %tpc, %l6
503 rdpr %tnpc, %l7
504 wrpr %g1, 0, %tnpc
505 done
506
507 /* We need to carefully read the error status, ACK
508 * the errors, prevent recursive traps, and pass the
509 * information on to C code for logging.
510 *
511 * We pass the AFAR in as-is, and we encode the status
512 * information as described in asm-sparc64/sfafsr.h
513 */
514 .globl __spitfire_access_error
515__spitfire_access_error:
516 /* Disable ESTATE error reporting so that we do not
517 * take recursive traps and RED state the processor.
518 */
519 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
520 membar #Sync
521
522 mov UDBE_UE, %g1
523 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
524
525 /* __spitfire_cee_trap branches here with AFSR in %g4 and
526 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
527 * ESTATE Error Enable register.
528 */
529__spitfire_cee_trap_continue:
530 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
531
532 rdpr %tt, %g3
533 and %g3, 0x1ff, %g3 ! Paranoia
534 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
535 or %g4, %g3, %g4
536 rdpr %tl, %g3
537 cmp %g3, 1
538 mov 1, %g3
539 bleu %xcc, 1f
540 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
541
542 or %g4, %g3, %g4
543
544 /* Read in the UDB error register state, clearing the
545 * sticky error bits as-needed. We only clear them if
546 * the UE bit is set. Likewise, __spitfire_cee_trap
547 * below will only do so if the CE bit is set.
548 *
549 * NOTE: UltraSparc-I/II have high and low UDB error
550 * registers, corresponding to the two UDB units
551 * present on those chips. UltraSparc-IIi only
552 * has a single UDB, called "SDB" in the manual.
553 * For IIi the upper UDB register always reads
554 * as zero so for our purposes things will just
555 * work with the checks below.
556 */
5571: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
558 and %g3, 0x3ff, %g7 ! Paranoia
559 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
560 or %g4, %g7, %g4
561 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
562 be,pn %xcc, 1f
563 nop
564 stxa %g3, [%g0] ASI_UDB_ERROR_W
565 membar #Sync
566
5671: mov 0x18, %g3
568 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
569 and %g3, 0x3ff, %g7 ! Paranoia
570 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
571 or %g4, %g7, %g4
572 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
573 be,pn %xcc, 1f
574 nop
575 mov 0x18, %g7
576 stxa %g3, [%g7] ASI_UDB_ERROR_W
577 membar #Sync
578
5791: /* Ok, now that we've latched the error state,
580 * clear the sticky bits in the AFSR.
581 */
582 stxa %g4, [%g0] ASI_AFSR
583 membar #Sync
584
585 rdpr %tl, %g2
586 cmp %g2, 1
587 rdpr %pil, %g2
588 bleu,pt %xcc, 1f
589 wrpr %g0, 15, %pil
590
591 ba,pt %xcc, etraptl1
592 rd %pc, %g7
593
594 ba,pt %xcc, 2f
595 nop
596
5971: ba,pt %xcc, etrap_irq
598 rd %pc, %g7
599
6002:
601#ifdef CONFIG_TRACE_IRQFLAGS
602 call trace_hardirqs_off
603 nop
604#endif
605 mov %l4, %o1
606 mov %l5, %o2
607 call spitfire_access_error
608 add %sp, PTREGS_OFF, %o0
609 ba,pt %xcc, rtrap
610 nop
611
612 /* This is the trap handler entry point for ECC correctable
613 * errors. They are corrected, but we listen for the trap
614 * so that the event can be logged.
615 *
616 * Disrupting errors are either:
617 * 1) single-bit ECC errors during UDB reads to system
618 * memory
619 * 2) data parity errors during write-back events
620 *
621 * As far as I can make out from the manual, the CEE trap
622 * is only for correctable errors during memory read
623 * accesses by the front-end of the processor.
624 *
625 * The code below is only for trap level 1 CEE events,
626 * as it is the only situation where we can safely record
627 * and log. For trap level >1 we just clear the CE bit
628 * in the AFSR and return.
629 *
630 * This is just like __spiftire_access_error above, but it
631 * specifically handles correctable errors. If an
632 * uncorrectable error is indicated in the AFSR we
633 * will branch directly above to __spitfire_access_error
634 * to handle it instead. Uncorrectable therefore takes
635 * priority over correctable, and the error logging
636 * C code will notice this case by inspecting the
637 * trap type.
638 */
639 .globl __spitfire_cee_trap
640__spitfire_cee_trap:
641 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
642 mov 1, %g3
643 sllx %g3, SFAFSR_UE_SHIFT, %g3
644 andcc %g4, %g3, %g0 ! Check for UE
645 bne,pn %xcc, __spitfire_access_error
646 nop
647
648 /* Ok, in this case we only have a correctable error.
649 * Indicate we only wish to capture that state in register
650 * %g1, and we only disable CE error reporting unlike UE
651 * handling which disables all errors.
652 */
653 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
654 andn %g3, ESTATE_ERR_CE, %g3
655 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
656 membar #Sync
657
658 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
659 ba,pt %xcc, __spitfire_cee_trap_continue
660 mov UDBE_CE, %g1
661
662 .globl __spitfire_data_access_exception
663 .globl __spitfire_data_access_exception_tl1
664__spitfire_data_access_exception_tl1:
665 rdpr %pstate, %g4
666 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
667 mov TLB_SFSR, %g3
668 mov DMMU_SFAR, %g5
669 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
670 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
671 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
672 membar #Sync
673 rdpr %tt, %g3
674 cmp %g3, 0x80 ! first win spill/fill trap
675 blu,pn %xcc, 1f
676 cmp %g3, 0xff ! last win spill/fill trap
677 bgu,pn %xcc, 1f
678 nop
679 ba,pt %xcc, winfix_dax
680 rdpr %tpc, %g3
6811: sethi %hi(109f), %g7
682 ba,pt %xcc, etraptl1
683109: or %g7, %lo(109b), %g7
684 mov %l4, %o1
685 mov %l5, %o2
686 call spitfire_data_access_exception_tl1
687 add %sp, PTREGS_OFF, %o0
688 ba,pt %xcc, rtrap
689 nop
690
691__spitfire_data_access_exception:
692 rdpr %pstate, %g4
693 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
694 mov TLB_SFSR, %g3
695 mov DMMU_SFAR, %g5
696 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
697 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
698 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
699 membar #Sync
700 sethi %hi(109f), %g7
701 ba,pt %xcc, etrap
702109: or %g7, %lo(109b), %g7
703 mov %l4, %o1
704 mov %l5, %o2
705 call spitfire_data_access_exception
706 add %sp, PTREGS_OFF, %o0
707 ba,pt %xcc, rtrap
708 nop
709
710 .globl __spitfire_insn_access_exception
711 .globl __spitfire_insn_access_exception_tl1
712__spitfire_insn_access_exception_tl1:
713 rdpr %pstate, %g4
714 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
715 mov TLB_SFSR, %g3
716 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
717 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
718 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
719 membar #Sync
720 sethi %hi(109f), %g7
721 ba,pt %xcc, etraptl1
722109: or %g7, %lo(109b), %g7
723 mov %l4, %o1
724 mov %l5, %o2
725 call spitfire_insn_access_exception_tl1
726 add %sp, PTREGS_OFF, %o0
727 ba,pt %xcc, rtrap
728 nop
729
730__spitfire_insn_access_exception:
731 rdpr %pstate, %g4
732 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
733 mov TLB_SFSR, %g3
734 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
735 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
736 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
737 membar #Sync
738 sethi %hi(109f), %g7
739 ba,pt %xcc, etrap
740109: or %g7, %lo(109b), %g7
741 mov %l4, %o1
742 mov %l5, %o2
743 call spitfire_insn_access_exception
744 add %sp, PTREGS_OFF, %o0
745 ba,pt %xcc, rtrap
746 nop
747
748 /* These get patched into the trap table at boot time
749 * once we know we have a cheetah processor.
750 */
751 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
752cheetah_fecc_trap_vector:
753 membar #Sync
754 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
755 andn %g1, DCU_DC | DCU_IC, %g1
756 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
757 membar #Sync
758 sethi %hi(cheetah_fast_ecc), %g2
759 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
760 mov 0, %g1
761cheetah_fecc_trap_vector_tl1:
762 membar #Sync
763 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
764 andn %g1, DCU_DC | DCU_IC, %g1
765 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
766 membar #Sync
767 sethi %hi(cheetah_fast_ecc), %g2
768 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
769 mov 1, %g1
770 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
771cheetah_cee_trap_vector:
772 membar #Sync
773 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
774 andn %g1, DCU_IC, %g1
775 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
776 membar #Sync
777 sethi %hi(cheetah_cee), %g2
778 jmpl %g2 + %lo(cheetah_cee), %g0
779 mov 0, %g1
780cheetah_cee_trap_vector_tl1:
781 membar #Sync
782 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
783 andn %g1, DCU_IC, %g1
784 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
785 membar #Sync
786 sethi %hi(cheetah_cee), %g2
787 jmpl %g2 + %lo(cheetah_cee), %g0
788 mov 1, %g1
789 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
790cheetah_deferred_trap_vector:
791 membar #Sync
792 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
793 andn %g1, DCU_DC | DCU_IC, %g1;
794 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
795 membar #Sync;
796 sethi %hi(cheetah_deferred_trap), %g2
797 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
798 mov 0, %g1
799cheetah_deferred_trap_vector_tl1:
800 membar #Sync;
801 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
802 andn %g1, DCU_DC | DCU_IC, %g1;
803 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
804 membar #Sync;
805 sethi %hi(cheetah_deferred_trap), %g2
806 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
807 mov 1, %g1
808
809 /* Cheetah+ specific traps. These are for the new I/D cache parity
810 * error traps. The first argument to cheetah_plus_parity_handler
811 * is encoded as follows:
812 *
813 * Bit0: 0=dcache,1=icache
814 * Bit1: 0=recoverable,1=unrecoverable
815 */
816 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
817cheetah_plus_dcpe_trap_vector:
818 membar #Sync
819 sethi %hi(do_cheetah_plus_data_parity), %g7
820 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
821 nop
822 nop
823 nop
824 nop
825 nop
826
827do_cheetah_plus_data_parity:
828 rdpr %pil, %g2
829 wrpr %g0, 15, %pil
830 ba,pt %xcc, etrap_irq
831 rd %pc, %g7
832#ifdef CONFIG_TRACE_IRQFLAGS
833 call trace_hardirqs_off
834 nop
835#endif
836 mov 0x0, %o0
837 call cheetah_plus_parity_error
838 add %sp, PTREGS_OFF, %o1
839 ba,a,pt %xcc, rtrap_irq
840
841cheetah_plus_dcpe_trap_vector_tl1:
842 membar #Sync
843 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
844 sethi %hi(do_dcpe_tl1), %g3
845 jmpl %g3 + %lo(do_dcpe_tl1), %g0
846 nop
847 nop
848 nop
849 nop
850
851 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
852cheetah_plus_icpe_trap_vector:
853 membar #Sync
854 sethi %hi(do_cheetah_plus_insn_parity), %g7
855 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
856 nop
857 nop
858 nop
859 nop
860 nop
861
862do_cheetah_plus_insn_parity:
863 rdpr %pil, %g2
864 wrpr %g0, 15, %pil
865 ba,pt %xcc, etrap_irq
866 rd %pc, %g7
867#ifdef CONFIG_TRACE_IRQFLAGS
868 call trace_hardirqs_off
869 nop
870#endif
871 mov 0x1, %o0
872 call cheetah_plus_parity_error
873 add %sp, PTREGS_OFF, %o1
874 ba,a,pt %xcc, rtrap_irq
875
876cheetah_plus_icpe_trap_vector_tl1:
877 membar #Sync
878 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
879 sethi %hi(do_icpe_tl1), %g3
880 jmpl %g3 + %lo(do_icpe_tl1), %g0
881 nop
882 nop
883 nop
884 nop
885
886 /* If we take one of these traps when tl >= 1, then we
887 * jump to interrupt globals. If some trap level above us
888 * was also using interrupt globals, we cannot recover.
889 * We may use all interrupt global registers except %g6.
890 */
891 .globl do_dcpe_tl1, do_icpe_tl1
892do_dcpe_tl1:
893 rdpr %tl, %g1 ! Save original trap level
894 mov 1, %g2 ! Setup TSTATE checking loop
895 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
8961: wrpr %g2, %tl ! Set trap level to check
897 rdpr %tstate, %g4 ! Read TSTATE for this level
898 andcc %g4, %g3, %g0 ! Interrupt globals in use?
899 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
900 wrpr %g1, %tl ! Restore original trap level
901 add %g2, 1, %g2 ! Next trap level
902 cmp %g2, %g1 ! Hit them all yet?
903 ble,pt %icc, 1b ! Not yet
904 nop
905 wrpr %g1, %tl ! Restore original trap level
906do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
907 sethi %hi(dcache_parity_tl1_occurred), %g2
908 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
909 add %g1, 1, %g1
910 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
911 /* Reset D-cache parity */
912 sethi %hi(1 << 16), %g1 ! D-cache size
913 mov (1 << 5), %g2 ! D-cache line size
914 sub %g1, %g2, %g1 ! Move down 1 cacheline
9151: srl %g1, 14, %g3 ! Compute UTAG
916 membar #Sync
917 stxa %g3, [%g1] ASI_DCACHE_UTAG
918 membar #Sync
919 sub %g2, 8, %g3 ! 64-bit data word within line
9202: membar #Sync
921 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
922 membar #Sync
923 subcc %g3, 8, %g3 ! Next 64-bit data word
924 bge,pt %icc, 2b
925 nop
926 subcc %g1, %g2, %g1 ! Next cacheline
927 bge,pt %icc, 1b
928 nop
929 ba,pt %xcc, dcpe_icpe_tl1_common
930 nop
931
932do_dcpe_tl1_fatal:
933 sethi %hi(1f), %g7
934 ba,pt %xcc, etraptl1
9351: or %g7, %lo(1b), %g7
936 mov 0x2, %o0
937 call cheetah_plus_parity_error
938 add %sp, PTREGS_OFF, %o1
939 ba,pt %xcc, rtrap
940 nop
941
942do_icpe_tl1:
943 rdpr %tl, %g1 ! Save original trap level
944 mov 1, %g2 ! Setup TSTATE checking loop
945 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
9461: wrpr %g2, %tl ! Set trap level to check
947 rdpr %tstate, %g4 ! Read TSTATE for this level
948 andcc %g4, %g3, %g0 ! Interrupt globals in use?
949 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
950 wrpr %g1, %tl ! Restore original trap level
951 add %g2, 1, %g2 ! Next trap level
952 cmp %g2, %g1 ! Hit them all yet?
953 ble,pt %icc, 1b ! Not yet
954 nop
955 wrpr %g1, %tl ! Restore original trap level
956do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
957 sethi %hi(icache_parity_tl1_occurred), %g2
958 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
959 add %g1, 1, %g1
960 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
961 /* Flush I-cache */
962 sethi %hi(1 << 15), %g1 ! I-cache size
963 mov (1 << 5), %g2 ! I-cache line size
964 sub %g1, %g2, %g1
9651: or %g1, (2 << 3), %g3
966 stxa %g0, [%g3] ASI_IC_TAG
967 membar #Sync
968 subcc %g1, %g2, %g1
969 bge,pt %icc, 1b
970 nop
971 ba,pt %xcc, dcpe_icpe_tl1_common
972 nop
973
974do_icpe_tl1_fatal:
975 sethi %hi(1f), %g7
976 ba,pt %xcc, etraptl1
9771: or %g7, %lo(1b), %g7
978 mov 0x3, %o0
979 call cheetah_plus_parity_error
980 add %sp, PTREGS_OFF, %o1
981 ba,pt %xcc, rtrap
982 nop
983
984dcpe_icpe_tl1_common:
985 /* Flush D-cache, re-enable D/I caches in DCU and finally
986 * retry the trapping instruction.
987 */
988 sethi %hi(1 << 16), %g1 ! D-cache size
989 mov (1 << 5), %g2 ! D-cache line size
990 sub %g1, %g2, %g1
9911: stxa %g0, [%g1] ASI_DCACHE_TAG
992 membar #Sync
993 subcc %g1, %g2, %g1
994 bge,pt %icc, 1b
995 nop
996 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
997 or %g1, (DCU_DC | DCU_IC), %g1
998 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
999 membar #Sync
1000 retry
1001
1002 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1003 *
1004 * %g1: (TL>=0) ? 1 : 0
1005 * %g2: scratch
1006 * %g3: scratch
1007 * %g4: AFSR
1008 * %g5: AFAR
1009 * %g6: unused, will have current thread ptr after etrap
1010 * %g7: scratch
1011 */
1012__cheetah_log_error:
1013 /* Put "TL1" software bit into AFSR. */
1014 and %g1, 0x1, %g1
1015 sllx %g1, 63, %g2
1016 or %g4, %g2, %g4
1017
1018 /* Get log entry pointer for this cpu at this trap level. */
1019 BRANCH_IF_JALAPENO(g2,g3,50f)
1020 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1021 srlx %g2, 17, %g2
1022 ba,pt %xcc, 60f
1023 and %g2, 0x3ff, %g2
1024
102550: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1026 srlx %g2, 17, %g2
1027 and %g2, 0x1f, %g2
1028
102960: sllx %g2, 9, %g2
1030 sethi %hi(cheetah_error_log), %g3
1031 ldx [%g3 + %lo(cheetah_error_log)], %g3
1032 brz,pn %g3, 80f
1033 nop
1034
1035 add %g3, %g2, %g3
1036 sllx %g1, 8, %g1
1037 add %g3, %g1, %g1
1038
1039 /* %g1 holds pointer to the top of the logging scoreboard */
1040 ldx [%g1 + 0x0], %g7
1041 cmp %g7, -1
1042 bne,pn %xcc, 80f
1043 nop
1044
1045 stx %g4, [%g1 + 0x0]
1046 stx %g5, [%g1 + 0x8]
1047 add %g1, 0x10, %g1
1048
1049 /* %g1 now points to D-cache logging area */
1050 set 0x3ff8, %g2 /* DC_addr mask */
1051 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1052 srlx %g5, 12, %g3
1053 or %g3, 1, %g3 /* PHYS tag + valid */
1054
105510: ldxa [%g2] ASI_DCACHE_TAG, %g7
1056 cmp %g3, %g7 /* TAG match? */
1057 bne,pt %xcc, 13f
1058 nop
1059
1060 /* Yep, what we want, capture state. */
1061 stx %g2, [%g1 + 0x20]
1062 stx %g7, [%g1 + 0x28]
1063
1064 /* A membar Sync is required before and after utag access. */
1065 membar #Sync
1066 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1067 membar #Sync
1068 stx %g7, [%g1 + 0x30]
1069 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1070 stx %g7, [%g1 + 0x38]
1071 clr %g3
1072
107312: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1074 stx %g7, [%g1]
1075 add %g3, (1 << 5), %g3
1076 cmp %g3, (4 << 5)
1077 bl,pt %xcc, 12b
1078 add %g1, 0x8, %g1
1079
1080 ba,pt %xcc, 20f
1081 add %g1, 0x20, %g1
1082
108313: sethi %hi(1 << 14), %g7
1084 add %g2, %g7, %g2
1085 srlx %g2, 14, %g7
1086 cmp %g7, 4
1087 bl,pt %xcc, 10b
1088 nop
1089
1090 add %g1, 0x40, %g1
1091
1092 /* %g1 now points to I-cache logging area */
109320: set 0x1fe0, %g2 /* IC_addr mask */
1094 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1095 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1096 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1097 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1098
109921: ldxa [%g2] ASI_IC_TAG, %g7
1100 andn %g7, 0xff, %g7
1101 cmp %g3, %g7
1102 bne,pt %xcc, 23f
1103 nop
1104
1105 /* Yep, what we want, capture state. */
1106 stx %g2, [%g1 + 0x40]
1107 stx %g7, [%g1 + 0x48]
1108 add %g2, (1 << 3), %g2
1109 ldxa [%g2] ASI_IC_TAG, %g7
1110 add %g2, (1 << 3), %g2
1111 stx %g7, [%g1 + 0x50]
1112 ldxa [%g2] ASI_IC_TAG, %g7
1113 add %g2, (1 << 3), %g2
1114 stx %g7, [%g1 + 0x60]
1115 ldxa [%g2] ASI_IC_TAG, %g7
1116 stx %g7, [%g1 + 0x68]
1117 sub %g2, (3 << 3), %g2
1118 ldxa [%g2] ASI_IC_STAG, %g7
1119 stx %g7, [%g1 + 0x58]
1120 clr %g3
1121 srlx %g2, 2, %g2
1122
112322: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1124 stx %g7, [%g1]
1125 add %g3, (1 << 3), %g3
1126 cmp %g3, (8 << 3)
1127 bl,pt %xcc, 22b
1128 add %g1, 0x8, %g1
1129
1130 ba,pt %xcc, 30f
1131 add %g1, 0x30, %g1
1132
113323: sethi %hi(1 << 14), %g7
1134 add %g2, %g7, %g2
1135 srlx %g2, 14, %g7
1136 cmp %g7, 4
1137 bl,pt %xcc, 21b
1138 nop
1139
1140 add %g1, 0x70, %g1
1141
1142 /* %g1 now points to E-cache logging area */
114330: andn %g5, (32 - 1), %g2
1144 stx %g2, [%g1 + 0x20]
1145 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1146 stx %g7, [%g1 + 0x28]
1147 ldxa [%g2] ASI_EC_R, %g0
1148 clr %g3
1149
115031: ldxa [%g3] ASI_EC_DATA, %g7
1151 stx %g7, [%g1 + %g3]
1152 add %g3, 0x8, %g3
1153 cmp %g3, 0x20
1154
1155 bl,pt %xcc, 31b
1156 nop
115780:
1158 rdpr %tt, %g2
1159 cmp %g2, 0x70
1160 be c_fast_ecc
1161 cmp %g2, 0x63
1162 be c_cee
1163 nop
1164 ba,pt %xcc, c_deferred
1165
1166 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1167 * in the trap table. That code has done a memory barrier
1168 * and has disabled both the I-cache and D-cache in the DCU
1169 * control register. The I-cache is disabled so that we may
1170 * capture the corrupted cache line, and the D-cache is disabled
1171 * because corrupt data may have been placed there and we don't
1172 * want to reference it.
1173 *
1174 * %g1 is one if this trap occurred at %tl >= 1.
1175 *
1176 * Next, we turn off error reporting so that we don't recurse.
1177 */
1178 .globl cheetah_fast_ecc
1179cheetah_fast_ecc:
1180 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1181 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1182 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1183 membar #Sync
1184
1185 /* Fetch and clear AFSR/AFAR */
1186 ldxa [%g0] ASI_AFSR, %g4
1187 ldxa [%g0] ASI_AFAR, %g5
1188 stxa %g4, [%g0] ASI_AFSR
1189 membar #Sync
1190
1191 ba,pt %xcc, __cheetah_log_error
1192 nop
1193
1194c_fast_ecc:
1195 rdpr %pil, %g2
1196 wrpr %g0, 15, %pil
1197 ba,pt %xcc, etrap_irq
1198 rd %pc, %g7
1199#ifdef CONFIG_TRACE_IRQFLAGS
1200 call trace_hardirqs_off
1201 nop
1202#endif
1203 mov %l4, %o1
1204 mov %l5, %o2
1205 call cheetah_fecc_handler
1206 add %sp, PTREGS_OFF, %o0
1207 ba,a,pt %xcc, rtrap_irq
1208
1209 /* Our caller has disabled I-cache and performed membar Sync. */
1210 .globl cheetah_cee
1211cheetah_cee:
1212 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1213 andn %g2, ESTATE_ERROR_CEEN, %g2
1214 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1215 membar #Sync
1216
1217 /* Fetch and clear AFSR/AFAR */
1218 ldxa [%g0] ASI_AFSR, %g4
1219 ldxa [%g0] ASI_AFAR, %g5
1220 stxa %g4, [%g0] ASI_AFSR
1221 membar #Sync
1222
1223 ba,pt %xcc, __cheetah_log_error
1224 nop
1225
1226c_cee:
1227 rdpr %pil, %g2
1228 wrpr %g0, 15, %pil
1229 ba,pt %xcc, etrap_irq
1230 rd %pc, %g7
1231#ifdef CONFIG_TRACE_IRQFLAGS
1232 call trace_hardirqs_off
1233 nop
1234#endif
1235 mov %l4, %o1
1236 mov %l5, %o2
1237 call cheetah_cee_handler
1238 add %sp, PTREGS_OFF, %o0
1239 ba,a,pt %xcc, rtrap_irq
1240
1241 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1242 .globl cheetah_deferred_trap
1243cheetah_deferred_trap:
1244 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1245 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1246 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1247 membar #Sync
1248
1249 /* Fetch and clear AFSR/AFAR */
1250 ldxa [%g0] ASI_AFSR, %g4
1251 ldxa [%g0] ASI_AFAR, %g5
1252 stxa %g4, [%g0] ASI_AFSR
1253 membar #Sync
1254
1255 ba,pt %xcc, __cheetah_log_error
1256 nop
1257
1258c_deferred:
1259 rdpr %pil, %g2
1260 wrpr %g0, 15, %pil
1261 ba,pt %xcc, etrap_irq
1262 rd %pc, %g7
1263#ifdef CONFIG_TRACE_IRQFLAGS
1264 call trace_hardirqs_off
1265 nop
1266#endif
1267 mov %l4, %o1
1268 mov %l5, %o2
1269 call cheetah_deferred_handler
1270 add %sp, PTREGS_OFF, %o0
1271 ba,a,pt %xcc, rtrap_irq
1272
1273 .globl __do_privact
1274__do_privact:
1275 mov TLB_SFSR, %g3
1276 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1277 membar #Sync
1278 sethi %hi(109f), %g7
1279 ba,pt %xcc, etrap
1280109: or %g7, %lo(109b), %g7
1281 call do_privact
1282 add %sp, PTREGS_OFF, %o0
1283 ba,pt %xcc, rtrap
1284 nop
1285
1286 .globl do_mna
1287do_mna:
1288 rdpr %tl, %g3
1289 cmp %g3, 1
1290
1291 /* Setup %g4/%g5 now as they are used in the
1292 * winfixup code.
1293 */
1294 mov TLB_SFSR, %g3
1295 mov DMMU_SFAR, %g4
1296 ldxa [%g4] ASI_DMMU, %g4
1297 ldxa [%g3] ASI_DMMU, %g5
1298 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1299 membar #Sync
1300 bgu,pn %icc, winfix_mna
1301 rdpr %tpc, %g3
1302
13031: sethi %hi(109f), %g7
1304 ba,pt %xcc, etrap
1305109: or %g7, %lo(109b), %g7
1306 mov %l4, %o1
1307 mov %l5, %o2
1308 call mem_address_unaligned
1309 add %sp, PTREGS_OFF, %o0
1310 ba,pt %xcc, rtrap
1311 nop
1312
1313 .globl do_lddfmna
1314do_lddfmna:
1315 sethi %hi(109f), %g7
1316 mov TLB_SFSR, %g4
1317 ldxa [%g4] ASI_DMMU, %g5
1318 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1319 membar #Sync
1320 mov DMMU_SFAR, %g4
1321 ldxa [%g4] ASI_DMMU, %g4
1322 ba,pt %xcc, etrap
1323109: or %g7, %lo(109b), %g7
1324 mov %l4, %o1
1325 mov %l5, %o2
1326 call handle_lddfmna
1327 add %sp, PTREGS_OFF, %o0
1328 ba,pt %xcc, rtrap
1329 nop
1330
1331 .globl do_stdfmna
1332do_stdfmna:
1333 sethi %hi(109f), %g7
1334 mov TLB_SFSR, %g4
1335 ldxa [%g4] ASI_DMMU, %g5
1336 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1337 membar #Sync
1338 mov DMMU_SFAR, %g4
1339 ldxa [%g4] ASI_DMMU, %g4
1340 ba,pt %xcc, etrap
1341109: or %g7, %lo(109b), %g7
1342 mov %l4, %o1
1343 mov %l5, %o2
1344 call handle_stdfmna
1345 add %sp, PTREGS_OFF, %o0
1346 ba,pt %xcc, rtrap
1347 nop
1348
1349 .globl breakpoint_trap
1350breakpoint_trap:
1351 call sparc_breakpoint
1352 add %sp, PTREGS_OFF, %o0
1353 ba,pt %xcc, rtrap
1354 nop
1355
1356 /* SunOS's execv() call only specifies the argv argument, the
1357 * environment settings are the same as the calling processes.
1358 */
1359 .globl sunos_execv
1360sys_execve:
1361 sethi %hi(sparc_execve), %g1
1362 ba,pt %xcc, execve_merge
1363 or %g1, %lo(sparc_execve), %g1
1364#ifdef CONFIG_COMPAT
1365 .globl sys_execve
1366sunos_execv:
1367 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1368 .globl sys32_execve
1369sys32_execve:
1370 sethi %hi(sparc32_execve), %g1
1371 or %g1, %lo(sparc32_execve), %g1
1372#endif
1373execve_merge:
1374 flushw
1375 jmpl %g1, %g0
1376 add %sp, PTREGS_OFF, %o0
1377
1378 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1379 .globl sys_rt_sigreturn
1380 .globl sys_ptrace
1381 .globl sys_sigaltstack
1382 .align 32
1383sys_pipe: ba,pt %xcc, sparc_pipe
1384 add %sp, PTREGS_OFF, %o0
1385sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1386 add %sp, PTREGS_OFF, %o0
1387sys_memory_ordering:
1388 ba,pt %xcc, sparc_memory_ordering
1389 add %sp, PTREGS_OFF, %o1
1390sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1391 add %i6, STACK_BIAS, %o2
1392#ifdef CONFIG_COMPAT
1393 .globl sys32_sigstack
1394sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1395 mov %i6, %o2
1396 .globl sys32_sigaltstack
1397sys32_sigaltstack:
1398 ba,pt %xcc, do_sys32_sigaltstack
1399 mov %i6, %o2
1400#endif
1401 .align 32
1402#ifdef CONFIG_COMPAT
1403 .globl sys32_sigreturn
1404sys32_sigreturn:
1405 add %sp, PTREGS_OFF, %o0
1406 call do_sigreturn32
1407 add %o7, 1f-.-4, %o7
1408 nop
1409#endif
1410sys_rt_sigreturn:
1411 add %sp, PTREGS_OFF, %o0
1412 call do_rt_sigreturn
1413 add %o7, 1f-.-4, %o7
1414 nop
1415#ifdef CONFIG_COMPAT
1416 .globl sys32_rt_sigreturn
1417sys32_rt_sigreturn:
1418 add %sp, PTREGS_OFF, %o0
1419 call do_rt_sigreturn32
1420 add %o7, 1f-.-4, %o7
1421 nop
1422#endif
1423 .align 32
14241: ldx [%curptr + TI_FLAGS], %l5
1425 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1426 be,pt %icc, rtrap
1427 nop
1428 add %sp, PTREGS_OFF, %o0
1429 call syscall_trace
1430 mov 1, %o1
1431
1432 ba,pt %xcc, rtrap
1433 nop
1434
1435 /* This is how fork() was meant to be done, 8 instruction entry.
1436 *
1437 * I questioned the following code briefly, let me clear things
1438 * up so you must not reason on it like I did.
1439 *
1440 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1441 * need it here because the only piece of window state we copy to
1442 * the child is the CWP register. Even if the parent sleeps,
1443 * we are safe because we stuck it into pt_regs of the parent
1444 * so it will not change.
1445 *
1446 * XXX This raises the question, whether we can do the same on
1447 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1448 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1449 * XXX fork_kwim in UREG_G1 (global registers are considered
1450 * XXX volatile across a system call in the sparc ABI I think
1451 * XXX if it isn't we can use regs->y instead, anyone who depends
1452 * XXX upon the Y register being preserved across a fork deserves
1453 * XXX to lose).
1454 *
1455 * In fact we should take advantage of that fact for other things
1456 * during system calls...
1457 */
1458 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1459 .globl ret_from_syscall
1460 .align 32
1461sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1462 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1463 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1464 ba,pt %xcc, sys_clone
1465sys_fork: clr %o1
1466 mov SIGCHLD, %o0
1467sys_clone: flushw
1468 movrz %o1, %fp, %o1
1469 mov 0, %o3
1470 ba,pt %xcc, sparc_do_fork
1471 add %sp, PTREGS_OFF, %o2
1472ret_from_syscall:
1473 /* Clear current_thread_info()->new_child, and
1474 * check performance counter stuff too.
1475 */
1476 stb %g0, [%g6 + TI_NEW_CHILD]
1477 ldx [%g6 + TI_FLAGS], %l0
1478 call schedule_tail
1479 mov %g7, %o0
1480 andcc %l0, _TIF_PERFCTR, %g0
1481 be,pt %icc, 1f
1482 nop
1483 ldx [%g6 + TI_PCR], %o7
1484 wr %g0, %o7, %pcr
1485
1486 /* Blackbird errata workaround. See commentary in
1487 * smp.c:smp_percpu_timer_interrupt() for more
1488 * information.
1489 */
1490 ba,pt %xcc, 99f
1491 nop
1492 .align 64
149399: wr %g0, %g0, %pic
1494 rd %pic, %g0
1495
14961: b,pt %xcc, ret_sys_call
1497 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1498sparc_exit: rdpr %pstate, %g2
1499 wrpr %g2, PSTATE_IE, %pstate
1500 rdpr %otherwin, %g1
1501 rdpr %cansave, %g3
1502 add %g3, %g1, %g3
1503 wrpr %g3, 0x0, %cansave
1504 wrpr %g0, 0x0, %otherwin
1505 wrpr %g2, 0x0, %pstate
1506 ba,pt %xcc, sys_exit
1507 stb %g0, [%g6 + TI_WSAVED]
1508
1509linux_sparc_ni_syscall:
1510 sethi %hi(sys_ni_syscall), %l7
1511 b,pt %xcc, 4f
1512 or %l7, %lo(sys_ni_syscall), %l7
1513
1514linux_syscall_trace32:
1515 add %sp, PTREGS_OFF, %o0
1516 call syscall_trace
1517 clr %o1
1518 srl %i0, 0, %o0
1519 srl %i4, 0, %o4
1520 srl %i1, 0, %o1
1521 srl %i2, 0, %o2
1522 b,pt %xcc, 2f
1523 srl %i3, 0, %o3
1524
1525linux_syscall_trace:
1526 add %sp, PTREGS_OFF, %o0
1527 call syscall_trace
1528 clr %o1
1529 mov %i0, %o0
1530 mov %i1, %o1
1531 mov %i2, %o2
1532 mov %i3, %o3
1533 b,pt %xcc, 2f
1534 mov %i4, %o4
1535
1536
1537 /* Linux 32-bit system calls enter here... */
1538 .align 32
1539 .globl linux_sparc_syscall32
1540linux_sparc_syscall32:
1541 /* Direct access to user regs, much faster. */
1542 cmp %g1, NR_SYSCALLS ! IEU1 Group
1543 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1544 srl %i0, 0, %o0 ! IEU0
1545 sll %g1, 2, %l4 ! IEU0 Group
1546 srl %i4, 0, %o4 ! IEU1
1547 lduw [%l7 + %l4], %l7 ! Load
1548 srl %i1, 0, %o1 ! IEU0 Group
1549 ldx [%curptr + TI_FLAGS], %l0 ! Load
1550
1551 srl %i5, 0, %o5 ! IEU1
1552 srl %i2, 0, %o2 ! IEU0 Group
1553 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1554 bne,pn %icc, linux_syscall_trace32 ! CTI
1555 mov %i0, %l5 ! IEU1
1556 call %l7 ! CTI Group brk forced
1557 srl %i3, 0, %o3 ! IEU0
1558 ba,a,pt %xcc, 3f
1559
1560 /* Linux native system calls enter here... */
1561 .align 32
1562 .globl linux_sparc_syscall
1563linux_sparc_syscall:
1564 /* Direct access to user regs, much faster. */
1565 cmp %g1, NR_SYSCALLS ! IEU1 Group
1566 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1567 mov %i0, %o0 ! IEU0
1568 sll %g1, 2, %l4 ! IEU0 Group
1569 mov %i1, %o1 ! IEU1
1570 lduw [%l7 + %l4], %l7 ! Load
15714: mov %i2, %o2 ! IEU0 Group
1572 ldx [%curptr + TI_FLAGS], %l0 ! Load
1573
1574 mov %i3, %o3 ! IEU1
1575 mov %i4, %o4 ! IEU0 Group
1576 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1577 bne,pn %icc, linux_syscall_trace ! CTI Group
1578 mov %i0, %l5 ! IEU0
15792: call %l7 ! CTI Group brk forced
1580 mov %i5, %o5 ! IEU0
1581 nop
1582
15833: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1584ret_sys_call:
1585 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1586 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1587 sra %o0, 0, %o0
1588 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1589 sllx %g2, 32, %g2
1590
1591 /* Check if force_successful_syscall_return()
1592 * was invoked.
1593 */
1594 ldub [%curptr + TI_SYS_NOERROR], %l2
1595 brnz,a,pn %l2, 80f
1596 stb %g0, [%curptr + TI_SYS_NOERROR]
1597
1598 cmp %o0, -ERESTART_RESTARTBLOCK
1599 bgeu,pn %xcc, 1f
1600 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
160180:
1602 /* System call success, clear Carry condition code. */
1603 andn %g3, %g2, %g3
1604 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1605 bne,pn %icc, linux_syscall_trace2
1606 add %l1, 0x4, %l2 ! npc = npc+4
1607 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1608 ba,pt %xcc, rtrap
1609 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1610
16111:
1612 /* System call failure, set Carry condition code.
1613 * Also, get abs(errno) to return to the process.
1614 */
1615 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1616 sub %g0, %o0, %o0
1617 or %g3, %g2, %g3
1618 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1619 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1620 bne,pn %icc, linux_syscall_trace2
1621 add %l1, 0x4, %l2 ! npc = npc+4
1622 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1623
1624 b,pt %xcc, rtrap
1625 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1626linux_syscall_trace2:
1627 add %sp, PTREGS_OFF, %o0
1628 call syscall_trace
1629 mov 1, %o1
1630 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1631 ba,pt %xcc, rtrap
1632 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1633
1634 .align 32
1635 .globl __flushw_user
1636__flushw_user:
1637 rdpr %otherwin, %g1
1638 brz,pn %g1, 2f
1639 clr %g2
16401: save %sp, -128, %sp
1641 rdpr %otherwin, %g1
1642 brnz,pt %g1, 1b
1643 add %g2, 1, %g2
16441: sub %g2, 1, %g2
1645 brnz,pt %g2, 1b
1646 restore %g0, %g0, %g0
16472: retl
1648 nop
1649
1650 /* Flush %fp and %i7 to the stack for all register
1651 * windows active inside of the cpu. This allows
1652 * show_stack_trace() to avoid using an expensive
1653 * 'flushw'.
1654 */
1655 .globl stack_trace_flush
1656 .type stack_trace_flush,#function
1657stack_trace_flush:
1658 rdpr %pstate, %o0
1659 wrpr %o0, PSTATE_IE, %pstate
1660
1661 rdpr %cwp, %g1
1662 rdpr %canrestore, %g2
1663 sub %g1, 1, %g3
1664
16651: brz,pn %g2, 2f
1666 sub %g2, 1, %g2
1667 wrpr %g3, %cwp
1668 stx %fp, [%sp + STACK_BIAS + RW_V9_I6]
1669 stx %i7, [%sp + STACK_BIAS + RW_V9_I7]
1670 ba,pt %xcc, 1b
1671 sub %g3, 1, %g3
1672
16732: wrpr %g1, %cwp
1674 wrpr %o0, %pstate
1675
1676 retl
1677 nop
1678 .size stack_trace_flush,.-stack_trace_flush
1679
1680#ifdef CONFIG_SMP
1681 .globl hard_smp_processor_id
1682hard_smp_processor_id:
1683#endif
1684 .globl real_hard_smp_processor_id
1685real_hard_smp_processor_id:
1686 __GET_CPUID(%o0)
1687 retl
1688 nop
1689
1690 /* %o0: devhandle
1691 * %o1: devino
1692 *
1693 * returns %o0: sysino
1694 */
1695 .globl sun4v_devino_to_sysino
1696 .type sun4v_devino_to_sysino,#function
1697sun4v_devino_to_sysino:
1698 mov HV_FAST_INTR_DEVINO2SYSINO, %o5
1699 ta HV_FAST_TRAP
1700 retl
1701 mov %o1, %o0
1702 .size sun4v_devino_to_sysino, .-sun4v_devino_to_sysino
1703
1704 /* %o0: sysino
1705 *
1706 * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1707 */
1708 .globl sun4v_intr_getenabled
1709 .type sun4v_intr_getenabled,#function
1710sun4v_intr_getenabled:
1711 mov HV_FAST_INTR_GETENABLED, %o5
1712 ta HV_FAST_TRAP
1713 retl
1714 mov %o1, %o0
1715 .size sun4v_intr_getenabled, .-sun4v_intr_getenabled
1716
1717 /* %o0: sysino
1718 * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1719 */
1720 .globl sun4v_intr_setenabled
1721 .type sun4v_intr_setenabled,#function
1722sun4v_intr_setenabled:
1723 mov HV_FAST_INTR_SETENABLED, %o5
1724 ta HV_FAST_TRAP
1725 retl
1726 nop
1727 .size sun4v_intr_setenabled, .-sun4v_intr_setenabled
1728
1729 /* %o0: sysino
1730 *
1731 * returns %o0: intr_state (HV_INTR_STATE_*)
1732 */
1733 .globl sun4v_intr_getstate
1734 .type sun4v_intr_getstate,#function
1735sun4v_intr_getstate:
1736 mov HV_FAST_INTR_GETSTATE, %o5
1737 ta HV_FAST_TRAP
1738 retl
1739 mov %o1, %o0
1740 .size sun4v_intr_getstate, .-sun4v_intr_getstate
1741
1742 /* %o0: sysino
1743 * %o1: intr_state (HV_INTR_STATE_*)
1744 */
1745 .globl sun4v_intr_setstate
1746 .type sun4v_intr_setstate,#function
1747sun4v_intr_setstate:
1748 mov HV_FAST_INTR_SETSTATE, %o5
1749 ta HV_FAST_TRAP
1750 retl
1751 nop
1752 .size sun4v_intr_setstate, .-sun4v_intr_setstate
1753
1754 /* %o0: sysino
1755 *
1756 * returns %o0: cpuid
1757 */
1758 .globl sun4v_intr_gettarget
1759 .type sun4v_intr_gettarget,#function
1760sun4v_intr_gettarget:
1761 mov HV_FAST_INTR_GETTARGET, %o5
1762 ta HV_FAST_TRAP
1763 retl
1764 mov %o1, %o0
1765 .size sun4v_intr_gettarget, .-sun4v_intr_gettarget
1766
1767 /* %o0: sysino
1768 * %o1: cpuid
1769 */
1770 .globl sun4v_intr_settarget
1771 .type sun4v_intr_settarget,#function
1772sun4v_intr_settarget:
1773 mov HV_FAST_INTR_SETTARGET, %o5
1774 ta HV_FAST_TRAP
1775 retl
1776 nop
1777 .size sun4v_intr_settarget, .-sun4v_intr_settarget
1778
1779 /* %o0: cpuid
1780 * %o1: pc
1781 * %o2: rtba
1782 * %o3: arg0
1783 *
1784 * returns %o0: status
1785 */
1786 .globl sun4v_cpu_start
1787 .type sun4v_cpu_start,#function
1788sun4v_cpu_start:
1789 mov HV_FAST_CPU_START, %o5
1790 ta HV_FAST_TRAP
1791 retl
1792 nop
1793 .size sun4v_cpu_start, .-sun4v_cpu_start
1794
1795 /* %o0: cpuid
1796 *
1797 * returns %o0: status
1798 */
1799 .globl sun4v_cpu_stop
1800 .type sun4v_cpu_stop,#function
1801sun4v_cpu_stop:
1802 mov HV_FAST_CPU_STOP, %o5
1803 ta HV_FAST_TRAP
1804 retl
1805 nop
1806 .size sun4v_cpu_stop, .-sun4v_cpu_stop
1807
1808 /* returns %o0: status */
1809 .globl sun4v_cpu_yield
1810 .type sun4v_cpu_yield, #function
1811sun4v_cpu_yield:
1812 mov HV_FAST_CPU_YIELD, %o5
1813 ta HV_FAST_TRAP
1814 retl
1815 nop
1816 .size sun4v_cpu_yield, .-sun4v_cpu_yield
1817
1818 /* %o0: type
1819 * %o1: queue paddr
1820 * %o2: num queue entries
1821 *
1822 * returns %o0: status
1823 */
1824 .globl sun4v_cpu_qconf
1825 .type sun4v_cpu_qconf,#function
1826sun4v_cpu_qconf:
1827 mov HV_FAST_CPU_QCONF, %o5
1828 ta HV_FAST_TRAP
1829 retl
1830 nop
1831 .size sun4v_cpu_qconf, .-sun4v_cpu_qconf
1832
1833 /* %o0: num cpus in cpu list
1834 * %o1: cpu list paddr
1835 * %o2: mondo block paddr
1836 *
1837 * returns %o0: status
1838 */
1839 .globl sun4v_cpu_mondo_send
1840 .type sun4v_cpu_mondo_send,#function
1841sun4v_cpu_mondo_send:
1842 mov HV_FAST_CPU_MONDO_SEND, %o5
1843 ta HV_FAST_TRAP
1844 retl
1845 nop
1846 .size sun4v_cpu_mondo_send, .-sun4v_cpu_mondo_send
1847
1848 /* %o0: CPU ID
1849 *
1850 * returns %o0: -status if status non-zero, else
1851 * %o0: cpu state as HV_CPU_STATE_*
1852 */
1853 .globl sun4v_cpu_state
1854 .type sun4v_cpu_state,#function
1855sun4v_cpu_state:
1856 mov HV_FAST_CPU_STATE, %o5
1857 ta HV_FAST_TRAP
1858 brnz,pn %o0, 1f
1859 sub %g0, %o0, %o0
1860 mov %o1, %o0
18611: retl
1862 nop
1863 .size sun4v_cpu_state, .-sun4v_cpu_state
1864
1865 /* %o0: virtual address
1866 * %o1: must be zero
1867 * %o2: TTE
1868 * %o3: HV_MMU_* flags
1869 *
1870 * returns %o0: status
1871 */
1872 .globl sun4v_mmu_map_perm_addr
1873 .type sun4v_mmu_map_perm_addr,#function
1874sun4v_mmu_map_perm_addr:
1875 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
1876 ta HV_FAST_TRAP
1877 retl
1878 nop
1879 .size sun4v_mmu_map_perm_addr, .-sun4v_mmu_map_perm_addr
1880
1881 /* %o0: number of TSB descriptions
1882 * %o1: TSB descriptions real address
1883 *
1884 * returns %o0: status
1885 */
1886 .globl sun4v_mmu_tsb_ctx0
1887 .type sun4v_mmu_tsb_ctx0,#function
1888sun4v_mmu_tsb_ctx0:
1889 mov HV_FAST_MMU_TSB_CTX0, %o5
1890 ta HV_FAST_TRAP
1891 retl
1892 nop
1893 .size sun4v_mmu_tsb_ctx0, .-sun4v_mmu_tsb_ctx0
1894
1895 /* %o0: API group number
1896 * %o1: pointer to unsigned long major number storage
1897 * %o2: pointer to unsigned long minor number storage
1898 *
1899 * returns %o0: status
1900 */
1901 .globl sun4v_get_version
1902 .type sun4v_get_version,#function
1903sun4v_get_version:
1904 mov HV_CORE_GET_VER, %o5
1905 mov %o1, %o3
1906 mov %o2, %o4
1907 ta HV_CORE_TRAP
1908 stx %o1, [%o3]
1909 retl
1910 stx %o2, [%o4]
1911 .size sun4v_get_version, .-sun4v_get_version
1912
1913 /* %o0: API group number
1914 * %o1: desired major number
1915 * %o2: desired minor number
1916 * %o3: pointer to unsigned long actual minor number storage
1917 *
1918 * returns %o0: status
1919 */
1920 .globl sun4v_set_version
1921 .type sun4v_set_version,#function
1922sun4v_set_version:
1923 mov HV_CORE_SET_VER, %o5
1924 mov %o3, %o4
1925 ta HV_CORE_TRAP
1926 retl
1927 stx %o1, [%o4]
1928 .size sun4v_set_version, .-sun4v_set_version
1929
1930 /* %o0: pointer to unsigned long time
1931 *
1932 * returns %o0: status
1933 */
1934 .globl sun4v_tod_get
1935 .type sun4v_tod_get,#function
1936sun4v_tod_get:
1937 mov %o0, %o4
1938 mov HV_FAST_TOD_GET, %o5
1939 ta HV_FAST_TRAP
1940 stx %o1, [%o4]
1941 retl
1942 nop
1943 .size sun4v_tod_get, .-sun4v_tod_get
1944
1945 /* %o0: time
1946 *
1947 * returns %o0: status
1948 */
1949 .globl sun4v_tod_set
1950 .type sun4v_tod_set,#function
1951sun4v_tod_set:
1952 mov HV_FAST_TOD_SET, %o5
1953 ta HV_FAST_TRAP
1954 retl
1955 nop
1956 .size sun4v_tod_set, .-sun4v_tod_set
1957
1958 /* %o0: pointer to unsigned long status
1959 *
1960 * returns %o0: signed character
1961 */
1962 .globl sun4v_con_getchar
1963 .type sun4v_con_getchar,#function
1964sun4v_con_getchar:
1965 mov %o0, %o4
1966 mov HV_FAST_CONS_GETCHAR, %o5
1967 clr %o0
1968 clr %o1
1969 ta HV_FAST_TRAP
1970 stx %o0, [%o4]
1971 retl
1972 sra %o1, 0, %o0
1973 .size sun4v_con_getchar, .-sun4v_con_getchar
1974
1975 /* %o0: signed long character
1976 *
1977 * returns %o0: status
1978 */
1979 .globl sun4v_con_putchar
1980 .type sun4v_con_putchar,#function
1981sun4v_con_putchar:
1982 mov HV_FAST_CONS_PUTCHAR, %o5
1983 ta HV_FAST_TRAP
1984 retl
1985 sra %o0, 0, %o0
1986 .size sun4v_con_putchar, .-sun4v_con_putchar
1987
1988 /* %o0: buffer real address
1989 * %o1: buffer size
1990 * %o2: pointer to unsigned long bytes_read
1991 *
1992 * returns %o0: status
1993 */
1994 .globl sun4v_con_read
1995 .type sun4v_con_read,#function
1996sun4v_con_read:
1997 mov %o2, %o4
1998 mov HV_FAST_CONS_READ, %o5
1999 ta HV_FAST_TRAP
2000 brnz %o0, 1f
2001 cmp %o1, -1 /* break */
2002 be,a,pn %icc, 1f
2003 mov %o1, %o0
2004 cmp %o1, -2 /* hup */
2005 be,a,pn %icc, 1f
2006 mov %o1, %o0
2007 stx %o1, [%o4]
20081: retl
2009 nop
2010 .size sun4v_con_read, .-sun4v_con_read
2011
2012 /* %o0: buffer real address
2013 * %o1: buffer size
2014 * %o2: pointer to unsigned long bytes_written
2015 *
2016 * returns %o0: status
2017 */
2018 .globl sun4v_con_write
2019 .type sun4v_con_write,#function
2020sun4v_con_write:
2021 mov %o2, %o4
2022 mov HV_FAST_CONS_WRITE, %o5
2023 ta HV_FAST_TRAP
2024 stx %o1, [%o4]
2025 retl
2026 nop
2027 .size sun4v_con_write, .-sun4v_con_write
2028
2029 /* %o0: soft state
2030 * %o1: address of description string
2031 *
2032 * returns %o0: status
2033 */
2034 .globl sun4v_mach_set_soft_state
2035 .type sun4v_mach_set_soft_state,#function
2036sun4v_mach_set_soft_state:
2037 mov HV_FAST_MACH_SET_SOFT_STATE, %o5
2038 ta HV_FAST_TRAP
2039 retl
2040 nop
2041 .size sun4v_mach_set_soft_state, .-sun4v_mach_set_soft_state
2042
2043 /* %o0: exit code
2044 *
2045 * Does not return.
2046 */
2047 .globl sun4v_mach_exit
2048 .type sun4v_mach_exit,#function
2049sun4v_mach_exit:
2050 mov HV_FAST_MACH_EXIT, %o5
2051 ta HV_FAST_TRAP
2052 retl
2053 nop
2054 .size sun4v_mach_exit, .-sun4v_mach_exit
2055
2056 /* %o0: buffer real address
2057 * %o1: buffer length
2058 * %o2: pointer to unsigned long real_buf_len
2059 *
2060 * returns %o0: status
2061 */
2062 .globl sun4v_mach_desc
2063 .type sun4v_mach_desc,#function
2064sun4v_mach_desc:
2065 mov %o2, %o4
2066 mov HV_FAST_MACH_DESC, %o5
2067 ta HV_FAST_TRAP
2068 stx %o1, [%o4]
2069 retl
2070 nop
2071 .size sun4v_mach_desc, .-sun4v_mach_desc
2072
2073 /* %o0: new timeout in milliseconds
2074 * %o1: pointer to unsigned long orig_timeout
2075 *
2076 * returns %o0: status
2077 */
2078 .globl sun4v_mach_set_watchdog
2079 .type sun4v_mach_set_watchdog,#function
2080sun4v_mach_set_watchdog:
2081 mov %o1, %o4
2082 mov HV_FAST_MACH_SET_WATCHDOG, %o5
2083 ta HV_FAST_TRAP
2084 stx %o1, [%o4]
2085 retl
2086 nop
2087 .size sun4v_mach_set_watchdog, .-sun4v_mach_set_watchdog
2088
2089 /* No inputs and does not return. */
2090 .globl sun4v_mach_sir
2091 .type sun4v_mach_sir,#function
2092sun4v_mach_sir:
2093 mov %o1, %o4
2094 mov HV_FAST_MACH_SIR, %o5
2095 ta HV_FAST_TRAP
2096 stx %o1, [%o4]
2097 retl
2098 nop
2099 .size sun4v_mach_sir, .-sun4v_mach_sir
2100
2101 /* %o0: channel
2102 * %o1: ra
2103 * %o2: num_entries
2104 *
2105 * returns %o0: status
2106 */
2107 .globl sun4v_ldc_tx_qconf
2108 .type sun4v_ldc_tx_qconf,#function
2109sun4v_ldc_tx_qconf:
2110 mov HV_FAST_LDC_TX_QCONF, %o5
2111 ta HV_FAST_TRAP
2112 retl
2113 nop
2114 .size sun4v_ldc_tx_qconf, .-sun4v_ldc_tx_qconf
2115
2116 /* %o0: channel
2117 * %o1: pointer to unsigned long ra
2118 * %o2: pointer to unsigned long num_entries
2119 *
2120 * returns %o0: status
2121 */
2122 .globl sun4v_ldc_tx_qinfo
2123 .type sun4v_ldc_tx_qinfo,#function
2124sun4v_ldc_tx_qinfo:
2125 mov %o1, %g1
2126 mov %o2, %g2
2127 mov HV_FAST_LDC_TX_QINFO, %o5
2128 ta HV_FAST_TRAP
2129 stx %o1, [%g1]
2130 stx %o2, [%g2]
2131 retl
2132 nop
2133 .size sun4v_ldc_tx_qinfo, .-sun4v_ldc_tx_qinfo
2134
2135 /* %o0: channel
2136 * %o1: pointer to unsigned long head_off
2137 * %o2: pointer to unsigned long tail_off
2138 * %o2: pointer to unsigned long chan_state
2139 *
2140 * returns %o0: status
2141 */
2142 .globl sun4v_ldc_tx_get_state
2143 .type sun4v_ldc_tx_get_state,#function
2144sun4v_ldc_tx_get_state:
2145 mov %o1, %g1
2146 mov %o2, %g2
2147 mov %o3, %g3
2148 mov HV_FAST_LDC_TX_GET_STATE, %o5
2149 ta HV_FAST_TRAP
2150 stx %o1, [%g1]
2151 stx %o2, [%g2]
2152 stx %o3, [%g3]
2153 retl
2154 nop
2155 .size sun4v_ldc_tx_get_state, .-sun4v_ldc_tx_get_state
2156
2157 /* %o0: channel
2158 * %o1: tail_off
2159 *
2160 * returns %o0: status
2161 */
2162 .globl sun4v_ldc_tx_set_qtail
2163 .type sun4v_ldc_tx_set_qtail,#function
2164sun4v_ldc_tx_set_qtail:
2165 mov HV_FAST_LDC_TX_SET_QTAIL, %o5
2166 ta HV_FAST_TRAP
2167 retl
2168 nop
2169 .size sun4v_ldc_tx_set_qtail, .-sun4v_ldc_tx_set_qtail
2170
2171 /* %o0: channel
2172 * %o1: ra
2173 * %o2: num_entries
2174 *
2175 * returns %o0: status
2176 */
2177 .globl sun4v_ldc_rx_qconf
2178 .type sun4v_ldc_rx_qconf,#function
2179sun4v_ldc_rx_qconf:
2180 mov HV_FAST_LDC_RX_QCONF, %o5
2181 ta HV_FAST_TRAP
2182 retl
2183 nop
2184 .size sun4v_ldc_rx_qconf, .-sun4v_ldc_rx_qconf
2185
2186 /* %o0: channel
2187 * %o1: pointer to unsigned long ra
2188 * %o2: pointer to unsigned long num_entries
2189 *
2190 * returns %o0: status
2191 */
2192 .globl sun4v_ldc_rx_qinfo
2193 .type sun4v_ldc_rx_qinfo,#function
2194sun4v_ldc_rx_qinfo:
2195 mov %o1, %g1
2196 mov %o2, %g2
2197 mov HV_FAST_LDC_RX_QINFO, %o5
2198 ta HV_FAST_TRAP
2199 stx %o1, [%g1]
2200 stx %o2, [%g2]
2201 retl
2202 nop
2203 .size sun4v_ldc_rx_qinfo, .-sun4v_ldc_rx_qinfo
2204
2205 /* %o0: channel
2206 * %o1: pointer to unsigned long head_off
2207 * %o2: pointer to unsigned long tail_off
2208 * %o2: pointer to unsigned long chan_state
2209 *
2210 * returns %o0: status
2211 */
2212 .globl sun4v_ldc_rx_get_state
2213 .type sun4v_ldc_rx_get_state,#function
2214sun4v_ldc_rx_get_state:
2215 mov %o1, %g1
2216 mov %o2, %g2
2217 mov %o3, %g3
2218 mov HV_FAST_LDC_RX_GET_STATE, %o5
2219 ta HV_FAST_TRAP
2220 stx %o1, [%g1]
2221 stx %o2, [%g2]
2222 stx %o3, [%g3]
2223 retl
2224 nop
2225 .size sun4v_ldc_rx_get_state, .-sun4v_ldc_rx_get_state
2226
2227 /* %o0: channel
2228 * %o1: head_off
2229 *
2230 * returns %o0: status
2231 */
2232 .globl sun4v_ldc_rx_set_qhead
2233 .type sun4v_ldc_rx_set_qhead,#function
2234sun4v_ldc_rx_set_qhead:
2235 mov HV_FAST_LDC_RX_SET_QHEAD, %o5
2236 ta HV_FAST_TRAP
2237 retl
2238 nop
2239 .size sun4v_ldc_rx_set_qhead, .-sun4v_ldc_rx_set_qhead
2240
2241 /* %o0: channel
2242 * %o1: ra
2243 * %o2: num_entries
2244 *
2245 * returns %o0: status
2246 */
2247 .globl sun4v_ldc_set_map_table
2248 .type sun4v_ldc_set_map_table,#function
2249sun4v_ldc_set_map_table:
2250 mov HV_FAST_LDC_SET_MAP_TABLE, %o5
2251 ta HV_FAST_TRAP
2252 retl
2253 nop
2254 .size sun4v_ldc_set_map_table, .-sun4v_ldc_set_map_table
2255
2256 /* %o0: channel
2257 * %o1: pointer to unsigned long ra
2258 * %o2: pointer to unsigned long num_entries
2259 *
2260 * returns %o0: status
2261 */
2262 .globl sun4v_ldc_get_map_table
2263 .type sun4v_ldc_get_map_table,#function
2264sun4v_ldc_get_map_table:
2265 mov %o1, %g1
2266 mov %o2, %g2
2267 mov HV_FAST_LDC_GET_MAP_TABLE, %o5
2268 ta HV_FAST_TRAP
2269 stx %o1, [%g1]
2270 stx %o2, [%g2]
2271 retl
2272 nop
2273 .size sun4v_ldc_get_map_table, .-sun4v_ldc_get_map_table
2274
2275 /* %o0: channel
2276 * %o1: dir_code
2277 * %o2: tgt_raddr
2278 * %o3: lcl_raddr
2279 * %o4: len
2280 * %o5: pointer to unsigned long actual_len
2281 *
2282 * returns %o0: status
2283 */
2284 .globl sun4v_ldc_copy
2285 .type sun4v_ldc_copy,#function
2286sun4v_ldc_copy:
2287 mov %o5, %g1
2288 mov HV_FAST_LDC_COPY, %o5
2289 ta HV_FAST_TRAP
2290 stx %o1, [%g1]
2291 retl
2292 nop
2293 .size sun4v_ldc_copy, .-sun4v_ldc_copy
2294
2295 /* %o0: channel
2296 * %o1: cookie
2297 * %o2: pointer to unsigned long ra
2298 * %o3: pointer to unsigned long perm
2299 *
2300 * returns %o0: status
2301 */
2302 .globl sun4v_ldc_mapin
2303 .type sun4v_ldc_mapin,#function
2304sun4v_ldc_mapin:
2305 mov %o2, %g1
2306 mov %o3, %g2
2307 mov HV_FAST_LDC_MAPIN, %o5
2308 ta HV_FAST_TRAP
2309 stx %o1, [%g1]
2310 stx %o2, [%g2]
2311 retl
2312 nop
2313 .size sun4v_ldc_mapin, .-sun4v_ldc_mapin
2314
2315 /* %o0: ra
2316 *
2317 * returns %o0: status
2318 */
2319 .globl sun4v_ldc_unmap
2320 .type sun4v_ldc_unmap,#function
2321sun4v_ldc_unmap:
2322 mov HV_FAST_LDC_UNMAP, %o5
2323 ta HV_FAST_TRAP
2324 retl
2325 nop
2326 .size sun4v_ldc_unmap, .-sun4v_ldc_unmap
2327
2328 /* %o0: channel
2329 * %o1: cookie
2330 * %o2: mte_cookie
2331 *
2332 * returns %o0: status
2333 */
2334 .globl sun4v_ldc_revoke
2335 .type sun4v_ldc_revoke,#function
2336sun4v_ldc_revoke:
2337 mov HV_FAST_LDC_REVOKE, %o5
2338 ta HV_FAST_TRAP
2339 retl
2340 nop
2341 .size sun4v_ldc_revoke, .-sun4v_ldc_revoke
2342
2343 /* %o0: device handle
2344 * %o1: device INO
2345 * %o2: pointer to unsigned long cookie
2346 *
2347 * returns %o0: status
2348 */
2349 .globl sun4v_vintr_get_cookie
2350 .type sun4v_vintr_get_cookie,#function
2351sun4v_vintr_get_cookie:
2352 mov %o2, %g1
2353 mov HV_FAST_VINTR_GET_COOKIE, %o5
2354 ta HV_FAST_TRAP
2355 stx %o1, [%g1]
2356 retl
2357 nop
2358 .size sun4v_vintr_get_cookie, .-sun4v_vintr_get_cookie
2359
2360 /* %o0: device handle
2361 * %o1: device INO
2362 * %o2: cookie
2363 *
2364 * returns %o0: status
2365 */
2366 .globl sun4v_vintr_set_cookie
2367 .type sun4v_vintr_set_cookie,#function
2368sun4v_vintr_set_cookie:
2369 mov HV_FAST_VINTR_SET_COOKIE, %o5
2370 ta HV_FAST_TRAP
2371 retl
2372 nop
2373 .size sun4v_vintr_set_cookie, .-sun4v_vintr_set_cookie
2374
2375 /* %o0: device handle
2376 * %o1: device INO
2377 * %o2: pointer to unsigned long valid_state
2378 *
2379 * returns %o0: status
2380 */
2381 .globl sun4v_vintr_get_valid
2382 .type sun4v_vintr_get_valid,#function
2383sun4v_vintr_get_valid:
2384 mov %o2, %g1
2385 mov HV_FAST_VINTR_GET_VALID, %o5
2386 ta HV_FAST_TRAP
2387 stx %o1, [%g1]
2388 retl
2389 nop
2390 .size sun4v_vintr_get_valid, .-sun4v_vintr_get_valid
2391
2392 /* %o0: device handle
2393 * %o1: device INO
2394 * %o2: valid_state
2395 *
2396 * returns %o0: status
2397 */
2398 .globl sun4v_vintr_set_valid
2399 .type sun4v_vintr_set_valid,#function
2400sun4v_vintr_set_valid:
2401 mov HV_FAST_VINTR_SET_VALID, %o5
2402 ta HV_FAST_TRAP
2403 retl
2404 nop
2405 .size sun4v_vintr_set_valid, .-sun4v_vintr_set_valid
2406
2407 /* %o0: device handle
2408 * %o1: device INO
2409 * %o2: pointer to unsigned long state
2410 *
2411 * returns %o0: status
2412 */
2413 .globl sun4v_vintr_get_state
2414 .type sun4v_vintr_get_state,#function
2415sun4v_vintr_get_state:
2416 mov %o2, %g1
2417 mov HV_FAST_VINTR_GET_STATE, %o5
2418 ta HV_FAST_TRAP
2419 stx %o1, [%g1]
2420 retl
2421 nop
2422 .size sun4v_vintr_get_state, .-sun4v_vintr_get_state
2423
2424 /* %o0: device handle
2425 * %o1: device INO
2426 * %o2: state
2427 *
2428 * returns %o0: status
2429 */
2430 .globl sun4v_vintr_set_state
2431 .type sun4v_vintr_set_state,#function
2432sun4v_vintr_set_state:
2433 mov HV_FAST_VINTR_SET_STATE, %o5
2434 ta HV_FAST_TRAP
2435 retl
2436 nop
2437 .size sun4v_vintr_set_state, .-sun4v_vintr_set_state
2438
2439 /* %o0: device handle
2440 * %o1: device INO
2441 * %o2: pointer to unsigned long cpuid
2442 *
2443 * returns %o0: status
2444 */
2445 .globl sun4v_vintr_get_target
2446 .type sun4v_vintr_get_target,#function
2447sun4v_vintr_get_target:
2448 mov %o2, %g1
2449 mov HV_FAST_VINTR_GET_TARGET, %o5
2450 ta HV_FAST_TRAP
2451 stx %o1, [%g1]
2452 retl
2453 nop
2454 .size sun4v_vintr_get_target, .-sun4v_vintr_get_target
2455
2456 /* %o0: device handle
2457 * %o1: device INO
2458 * %o2: cpuid
2459 *
2460 * returns %o0: status
2461 */
2462 .globl sun4v_vintr_set_target
2463 .type sun4v_vintr_set_target,#function
2464sun4v_vintr_set_target:
2465 mov HV_FAST_VINTR_SET_TARGET, %o5
2466 ta HV_FAST_TRAP
2467 retl
2468 nop
2469 .size sun4v_vintr_set_target, .-sun4v_vintr_set_target
2470
2471 /* %o0: NCS sub-function
2472 * %o1: sub-function arg real-address
2473 * %o2: sub-function arg size
2474 *
2475 * returns %o0: status
2476 */
2477 .globl sun4v_ncs_request
2478 .type sun4v_ncs_request,#function
2479sun4v_ncs_request:
2480 mov HV_FAST_NCS_REQUEST, %o5
2481 ta HV_FAST_TRAP
2482 retl
2483 nop
2484 .size sun4v_ncs_request, .-sun4v_ncs_request
2485
2486 .globl sun4v_svc_send
2487 .type sun4v_svc_send,#function
2488sun4v_svc_send:
2489 save %sp, -192, %sp
2490 mov %i0, %o0
2491 mov %i1, %o1
2492 mov %i2, %o2
2493 mov HV_FAST_SVC_SEND, %o5
2494 ta HV_FAST_TRAP
2495 stx %o1, [%i3]
2496 ret
2497 restore
2498 .size sun4v_svc_send, .-sun4v_svc_send
2499
2500 .globl sun4v_svc_recv
2501 .type sun4v_svc_recv,#function
2502sun4v_svc_recv:
2503 save %sp, -192, %sp
2504 mov %i0, %o0
2505 mov %i1, %o1
2506 mov %i2, %o2
2507 mov HV_FAST_SVC_RECV, %o5
2508 ta HV_FAST_TRAP
2509 stx %o1, [%i3]
2510 ret
2511 restore
2512 .size sun4v_svc_recv, .-sun4v_svc_recv
2513
2514 .globl sun4v_svc_getstatus
2515 .type sun4v_svc_getstatus,#function
2516sun4v_svc_getstatus:
2517 mov HV_FAST_SVC_GETSTATUS, %o5
2518 mov %o1, %o4
2519 ta HV_FAST_TRAP
2520 stx %o1, [%o4]
2521 retl
2522 nop
2523 .size sun4v_svc_getstatus, .-sun4v_svc_getstatus
2524
2525 .globl sun4v_svc_setstatus
2526 .type sun4v_svc_setstatus,#function
2527sun4v_svc_setstatus:
2528 mov HV_FAST_SVC_SETSTATUS, %o5
2529 ta HV_FAST_TRAP
2530 retl
2531 nop
2532 .size sun4v_svc_setstatus, .-sun4v_svc_setstatus
2533
2534 .globl sun4v_svc_clrstatus
2535 .type sun4v_svc_clrstatus,#function
2536sun4v_svc_clrstatus:
2537 mov HV_FAST_SVC_CLRSTATUS, %o5
2538 ta HV_FAST_TRAP
2539 retl
2540 nop
2541 .size sun4v_svc_clrstatus, .-sun4v_svc_clrstatus
2542
2543 .globl sun4v_mmustat_conf
2544 .type sun4v_mmustat_conf,#function
2545sun4v_mmustat_conf:
2546 mov %o1, %o4
2547 mov HV_FAST_MMUSTAT_CONF, %o5
2548 ta HV_FAST_TRAP
2549 stx %o1, [%o4]
2550 retl
2551 nop
2552 .size sun4v_mmustat_conf, .-sun4v_mmustat_conf
2553
2554 .globl sun4v_mmustat_info
2555 .type sun4v_mmustat_info,#function
2556sun4v_mmustat_info:
2557 mov %o0, %o4
2558 mov HV_FAST_MMUSTAT_INFO, %o5
2559 ta HV_FAST_TRAP
2560 stx %o1, [%o4]
2561 retl
2562 nop
2563 .size sun4v_mmustat_info, .-sun4v_mmustat_info
2564
2565 .globl sun4v_mmu_demap_all
2566 .type sun4v_mmu_demap_all,#function
2567sun4v_mmu_demap_all:
2568 clr %o0
2569 clr %o1
2570 mov HV_MMU_ALL, %o2
2571 mov HV_FAST_MMU_DEMAP_ALL, %o5
2572 ta HV_FAST_TRAP
2573 retl
2574 nop
2575 .size sun4v_mmu_demap_all, .-sun4v_mmu_demap_all
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 05:45:16 -0500