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authorDavid S. Miller <davem@sunset.davemloft.net>2005-09-21 21:50:51 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2005-09-21 21:50:51 -0400
commit2a7e2990340a1c42321d79dc99755683ea5a1026 (patch)
tree4423f305fd52c7a28a38f00cd826d01ad60f2e97 /arch/sparc64/kernel/dtlb_base.S
parentefb0372bbaf5b829ff8c39db372779928af542a7 (diff)
[SPARC64]: Move kernel TLB miss handling into a seperate file.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/dtlb_base.S')
-rw-r--r--arch/sparc64/kernel/dtlb_base.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/sparc64/kernel/dtlb_base.S b/arch/sparc64/kernel/dtlb_base.S
index ded2fed23fcc..702d349c1e88 100644
--- a/arch/sparc64/kernel/dtlb_base.S
+++ b/arch/sparc64/kernel/dtlb_base.S
@@ -71,7 +71,7 @@
71from_tl1_trap: 71from_tl1_trap:
72 rdpr %tl, %g5 ! For TL==3 test 72 rdpr %tl, %g5 ! For TL==3 test
73 CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset 73 CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset
74 be,pn %xcc, 3f ! Yep, special processing 74 be,pn %xcc, kvmap ! Yep, special processing
75 CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset 75 CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset
76 cmp %g5, 4 ! Last trap level? 76 cmp %g5, 4 ! Last trap level?
77 be,pn %xcc, longpath ! Yep, cannot risk VPTE miss 77 be,pn %xcc, longpath ! Yep, cannot risk VPTE miss
@@ -83,9 +83,9 @@ from_tl1_trap:
83 nop ! Delay-slot 83 nop ! Delay-slot
849: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB 849: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
85 retry ! Trap return 85 retry ! Trap return
863: brlz,pt %g4, 9b ! Kernel virtual map? 86 nop
87 xor %g2, %g4, %g5 ! Finish bit twiddles 87 nop
88 ba,a,pt %xcc, kvmap ! Yep, go check for obp/vmalloc 88 nop
89 89
90/* DTLB ** ICACHE line 3: winfixups+real_faults */ 90/* DTLB ** ICACHE line 3: winfixups+real_faults */
91longpath: 91longpath: