diff options
author | Jeff Garzik <jgarzik@pobox.com> | 2005-10-13 21:22:27 -0400 |
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committer | Jeff Garzik <jgarzik@pobox.com> | 2005-10-13 21:22:27 -0400 |
commit | 59aee3c2a1e69fe5062bd1facb72d6fcea3f3f8f (patch) | |
tree | b337d73229a69e399d4e4f7128b33ce734660e35 /arch/sparc64/kernel/dtlb_base.S | |
parent | 0d69ae5fb7eb9ba3b54cf0ba4ef5ae591f31eef7 (diff) | |
parent | 046d20b73960b7a2474b6d5e920d54c3fd7c23fe (diff) |
Merge branch 'master'
Diffstat (limited to 'arch/sparc64/kernel/dtlb_base.S')
-rw-r--r-- | arch/sparc64/kernel/dtlb_base.S | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/arch/sparc64/kernel/dtlb_base.S b/arch/sparc64/kernel/dtlb_base.S index 702d349c1e88..6528786840c0 100644 --- a/arch/sparc64/kernel/dtlb_base.S +++ b/arch/sparc64/kernel/dtlb_base.S | |||
@@ -53,19 +53,18 @@ | |||
53 | * be guaranteed to be 0 ... mmu_context.h does guarantee this | 53 | * be guaranteed to be 0 ... mmu_context.h does guarantee this |
54 | * by only using 10 bits in the hwcontext value. | 54 | * by only using 10 bits in the hwcontext value. |
55 | */ | 55 | */ |
56 | #define CREATE_VPTE_OFFSET1(r1, r2) | 56 | #define CREATE_VPTE_OFFSET1(r1, r2) nop |
57 | #define CREATE_VPTE_OFFSET2(r1, r2) \ | 57 | #define CREATE_VPTE_OFFSET2(r1, r2) \ |
58 | srax r1, 10, r2 | 58 | srax r1, 10, r2 |
59 | #define CREATE_VPTE_NOP nop | ||
60 | #else | 59 | #else |
61 | #define CREATE_VPTE_OFFSET1(r1, r2) \ | 60 | #define CREATE_VPTE_OFFSET1(r1, r2) \ |
62 | srax r1, PAGE_SHIFT, r2 | 61 | srax r1, PAGE_SHIFT, r2 |
63 | #define CREATE_VPTE_OFFSET2(r1, r2) \ | 62 | #define CREATE_VPTE_OFFSET2(r1, r2) \ |
64 | sllx r2, 3, r2 | 63 | sllx r2, 3, r2 |
65 | #define CREATE_VPTE_NOP | ||
66 | #endif | 64 | #endif |
67 | 65 | ||
68 | /* DTLB ** ICACHE line 1: Quick user TLB misses */ | 66 | /* DTLB ** ICACHE line 1: Quick user TLB misses */ |
67 | mov TLB_SFSR, %g1 | ||
69 | ldxa [%g1 + %g1] ASI_DMMU, %g4 ! Get TAG_ACCESS | 68 | ldxa [%g1 + %g1] ASI_DMMU, %g4 ! Get TAG_ACCESS |
70 | andcc %g4, TAG_CONTEXT_BITS, %g0 ! From Nucleus? | 69 | andcc %g4, TAG_CONTEXT_BITS, %g0 ! From Nucleus? |
71 | from_tl1_trap: | 70 | from_tl1_trap: |
@@ -74,18 +73,16 @@ from_tl1_trap: | |||
74 | be,pn %xcc, kvmap ! Yep, special processing | 73 | be,pn %xcc, kvmap ! Yep, special processing |
75 | CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset | 74 | CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset |
76 | cmp %g5, 4 ! Last trap level? | 75 | cmp %g5, 4 ! Last trap level? |
77 | be,pn %xcc, longpath ! Yep, cannot risk VPTE miss | ||
78 | nop ! delay slot | ||
79 | 76 | ||
80 | /* DTLB ** ICACHE line 2: User finish + quick kernel TLB misses */ | 77 | /* DTLB ** ICACHE line 2: User finish + quick kernel TLB misses */ |
78 | be,pn %xcc, longpath ! Yep, cannot risk VPTE miss | ||
79 | nop ! delay slot | ||
81 | ldxa [%g3 + %g6] ASI_S, %g5 ! Load VPTE | 80 | ldxa [%g3 + %g6] ASI_S, %g5 ! Load VPTE |
82 | 1: brgez,pn %g5, longpath ! Invalid, branch out | 81 | 1: brgez,pn %g5, longpath ! Invalid, branch out |
83 | nop ! Delay-slot | 82 | nop ! Delay-slot |
84 | 9: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB | 83 | 9: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB |
85 | retry ! Trap return | 84 | retry ! Trap return |
86 | nop | 85 | nop |
87 | nop | ||
88 | nop | ||
89 | 86 | ||
90 | /* DTLB ** ICACHE line 3: winfixups+real_faults */ | 87 | /* DTLB ** ICACHE line 3: winfixups+real_faults */ |
91 | longpath: | 88 | longpath: |
@@ -106,8 +103,7 @@ longpath: | |||
106 | nop | 103 | nop |
107 | nop | 104 | nop |
108 | nop | 105 | nop |
109 | CREATE_VPTE_NOP | 106 | nop |
110 | 107 | ||
111 | #undef CREATE_VPTE_OFFSET1 | 108 | #undef CREATE_VPTE_OFFSET1 |
112 | #undef CREATE_VPTE_OFFSET2 | 109 | #undef CREATE_VPTE_OFFSET2 |
113 | #undef CREATE_VPTE_NOP | ||