[SPARC64]: Probe D/I/E-cache config and use.

At boot time, determine the D-cache, I-cache and E-cache size and
line-size.  Use them in cache flushes when appropriate.

This change was motivated by discovering that the D-cache on
UltraSparc-IIIi and later are 64K not 32K, and the flushes done by the
Cheetah error handlers were assuming a 32K size.

There are still some pieces of code that are hard coding things and
will need to be fixed up at some point.

While we're here, fix the D-cache and I-cache parity error handlers
to run with interrupts disabled, and when the trap occurs at trap
level > 1 log the event via a counter displayed in /proc/cpuinfo.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 22 insertions, 0 deletions

diff --git a/arch/sparc64/kernel/devices.c b/arch/sparc64/kernel/devices.c
index d710274e516b..df9a1ca8fd77 100644
--- a/arch/sparc64/kernel/devices.c
+++ b/arch/sparc64/kernel/devices.c
@@ -135,6 +135,28 @@ void __init device_scan(void)
                 cpu_data(0).clock_tick = prom_getintdefault(cpu_node,
                                                             "clock-frequency",
                                                             0);
+                cpu_data(0).dcache_size = prom_getintdefault(cpu_node,
+                                                             "dcache-size",
+                                                             16 * 1024);
+                cpu_data(0).dcache_line_size =
+                        prom_getintdefault(cpu_node, "dcache-line-size", 32);
+                cpu_data(0).icache_size = prom_getintdefault(cpu_node,
+                                                             "icache-size",
+                                                             16 * 1024);
+                cpu_data(0).icache_line_size =
+                        prom_getintdefault(cpu_node, "icache-line-size", 32);
+                cpu_data(0).ecache_size = prom_getintdefault(cpu_node,
+                                                             "ecache-size",
+                                                             4 * 1024 * 1024);
+                cpu_data(0).ecache_line_size =
+                        prom_getintdefault(cpu_node, "ecache-line-size", 64);
+                printk("CPU[0]: Caches "
+                       "D[sz(%d):line_sz(%d)] "
+                       "I[sz(%d):line_sz(%d)] "
+                       "E[sz(%d):line_sz(%d)]\n",
+                       cpu_data(0).dcache_size, cpu_data(0).dcache_line_size,
+                       cpu_data(0).icache_size, cpu_data(0).icache_line_size,
+                       cpu_data(0).ecache_size, cpu_data(0).ecache_line_size);
         }
 #endif