diff options
author | David S. Miller <davem@davemloft.net> | 2009-09-10 10:13:26 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-09-10 10:13:26 -0400 |
commit | 660d13765f342ecb6e774fcbc35b64beb0a069da (patch) | |
tree | 95987ea10feb7546ec6539742c60a89a129a2e21 /arch/sparc/kernel | |
parent | 496c07e3b43475124d7f2d77fafbc1f5055abfee (diff) |
sparc64: Perf counter 'nop' event is not constant.
On Niagara-2, for example, it's going to be different. So make
it something specified in sparc_pmu.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel')
-rw-r--r-- | arch/sparc/kernel/perf_counter.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/sparc/kernel/perf_counter.c b/arch/sparc/kernel/perf_counter.c index 0cd5487b3413..f3b8ccca3c92 100644 --- a/arch/sparc/kernel/perf_counter.c +++ b/arch/sparc/kernel/perf_counter.c | |||
@@ -52,9 +52,6 @@ | |||
52 | #define PIC_UPPER_INDEX 0 | 52 | #define PIC_UPPER_INDEX 0 |
53 | #define PIC_LOWER_INDEX 1 | 53 | #define PIC_LOWER_INDEX 1 |
54 | 54 | ||
55 | #define PIC_UPPER_NOP 0x1c | ||
56 | #define PIC_LOWER_NOP 0x14 | ||
57 | |||
58 | struct cpu_hw_counters { | 55 | struct cpu_hw_counters { |
59 | struct perf_counter *counters[MAX_HWCOUNTERS]; | 56 | struct perf_counter *counters[MAX_HWCOUNTERS]; |
60 | unsigned long used_mask[BITS_TO_LONGS(MAX_HWCOUNTERS)]; | 57 | unsigned long used_mask[BITS_TO_LONGS(MAX_HWCOUNTERS)]; |
@@ -79,6 +76,8 @@ struct sparc_pmu { | |||
79 | int event_mask; | 76 | int event_mask; |
80 | int hv_bit; | 77 | int hv_bit; |
81 | int irq_bit; | 78 | int irq_bit; |
79 | int upper_nop; | ||
80 | int lower_nop; | ||
82 | }; | 81 | }; |
83 | 82 | ||
84 | static const struct perf_event_map ultra3i_perfmon_event_map[] = { | 83 | static const struct perf_event_map ultra3i_perfmon_event_map[] = { |
@@ -99,6 +98,8 @@ static const struct sparc_pmu ultra3i_pmu = { | |||
99 | .upper_shift = 11, | 98 | .upper_shift = 11, |
100 | .lower_shift = 4, | 99 | .lower_shift = 4, |
101 | .event_mask = 0x3f, | 100 | .event_mask = 0x3f, |
101 | .upper_nop = 0x1c, | ||
102 | .lower_nop = 0x14, | ||
102 | }; | 103 | }; |
103 | 104 | ||
104 | static const struct sparc_pmu *sparc_pmu __read_mostly; | 105 | static const struct sparc_pmu *sparc_pmu __read_mostly; |
@@ -120,7 +121,8 @@ static u64 mask_for_index(int idx) | |||
120 | static u64 nop_for_index(int idx) | 121 | static u64 nop_for_index(int idx) |
121 | { | 122 | { |
122 | return event_encoding(idx == PIC_UPPER_INDEX ? | 123 | return event_encoding(idx == PIC_UPPER_INDEX ? |
123 | PIC_UPPER_NOP : PIC_LOWER_NOP, idx); | 124 | sparc_pmu->upper_nop : |
125 | sparc_pmu->lower_nop, idx); | ||
124 | } | 126 | } |
125 | 127 | ||
126 | static inline void sparc_pmu_enable_counter(struct hw_perf_counter *hwc, | 128 | static inline void sparc_pmu_enable_counter(struct hw_perf_counter *hwc, |