aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sparc/kernel/prom_64.c
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2008-12-05 03:43:03 -0500
committerDavid S. Miller <davem@davemloft.net>2008-12-05 20:02:32 -0500
commit5fce09c6f636449d6df971971af1bd4328a21890 (patch)
tree0658a110c1c8824f59127884c7fbace87cf5e28f /arch/sparc/kernel/prom_64.c
parentefeac2f87609ab25dab329ce16876eb9110b2084 (diff)
sparc: Move irq_trans_init() and support code into seperate file.
All sparc64 specific, so only build this file on sparc64. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel/prom_64.c')
-rw-r--r--arch/sparc/kernel/prom_64.c830
1 files changed, 0 insertions, 830 deletions
diff --git a/arch/sparc/kernel/prom_64.c b/arch/sparc/kernel/prom_64.c
index 1c7b9d7b7889..d745b9f44d2d 100644
--- a/arch/sparc/kernel/prom_64.c
+++ b/arch/sparc/kernel/prom_64.c
@@ -51,836 +51,6 @@ void * __init prom_early_alloc(unsigned long size)
51 return ret; 51 return ret;
52} 52}
53 53
54#ifdef CONFIG_PCI
55/* PSYCHO interrupt mapping support. */
56#define PSYCHO_IMAP_A_SLOT0 0x0c00UL
57#define PSYCHO_IMAP_B_SLOT0 0x0c20UL
58static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
59{
60 unsigned int bus = (ino & 0x10) >> 4;
61 unsigned int slot = (ino & 0x0c) >> 2;
62
63 if (bus == 0)
64 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
65 else
66 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
67}
68
69#define PSYCHO_OBIO_IMAP_BASE 0x1000UL
70
71#define PSYCHO_ONBOARD_IRQ_BASE 0x20
72#define psycho_onboard_imap_offset(__ino) \
73 (PSYCHO_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
74
75#define PSYCHO_ICLR_A_SLOT0 0x1400UL
76#define PSYCHO_ICLR_SCSI 0x1800UL
77
78#define psycho_iclr_offset(ino) \
79 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
80 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
81
82static unsigned int psycho_irq_build(struct device_node *dp,
83 unsigned int ino,
84 void *_data)
85{
86 unsigned long controller_regs = (unsigned long) _data;
87 unsigned long imap, iclr;
88 unsigned long imap_off, iclr_off;
89 int inofixup = 0;
90
91 ino &= 0x3f;
92 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
93 /* PCI slot */
94 imap_off = psycho_pcislot_imap_offset(ino);
95 } else {
96 /* Onboard device */
97 imap_off = psycho_onboard_imap_offset(ino);
98 }
99
100 /* Now build the IRQ bucket. */
101 imap = controller_regs + imap_off;
102
103 iclr_off = psycho_iclr_offset(ino);
104 iclr = controller_regs + iclr_off;
105
106 if ((ino & 0x20) == 0)
107 inofixup = ino & 0x03;
108
109 return build_irq(inofixup, iclr, imap);
110}
111
112static void __init psycho_irq_trans_init(struct device_node *dp)
113{
114 const struct linux_prom64_registers *regs;
115
116 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
117 dp->irq_trans->irq_build = psycho_irq_build;
118
119 regs = of_get_property(dp, "reg", NULL);
120 dp->irq_trans->data = (void *) regs[2].phys_addr;
121}
122
123#define sabre_read(__reg) \
124({ u64 __ret; \
125 __asm__ __volatile__("ldxa [%1] %2, %0" \
126 : "=r" (__ret) \
127 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
128 : "memory"); \
129 __ret; \
130})
131
132struct sabre_irq_data {
133 unsigned long controller_regs;
134 unsigned int pci_first_busno;
135};
136#define SABRE_CONFIGSPACE 0x001000000UL
137#define SABRE_WRSYNC 0x1c20UL
138
139#define SABRE_CONFIG_BASE(CONFIG_SPACE) \
140 (CONFIG_SPACE | (1UL << 24))
141#define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
142 (((unsigned long)(BUS) << 16) | \
143 ((unsigned long)(DEVFN) << 8) | \
144 ((unsigned long)(REG)))
145
146/* When a device lives behind a bridge deeper in the PCI bus topology
147 * than APB, a special sequence must run to make sure all pending DMA
148 * transfers at the time of IRQ delivery are visible in the coherency
149 * domain by the cpu. This sequence is to perform a read on the far
150 * side of the non-APB bridge, then perform a read of Sabre's DMA
151 * write-sync register.
152 */
153static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
154{
155 unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
156 struct sabre_irq_data *irq_data = _arg2;
157 unsigned long controller_regs = irq_data->controller_regs;
158 unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
159 unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
160 unsigned int bus, devfn;
161 u16 _unused;
162
163 config_space = SABRE_CONFIG_BASE(config_space);
164
165 bus = (phys_hi >> 16) & 0xff;
166 devfn = (phys_hi >> 8) & 0xff;
167
168 config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
169
170 __asm__ __volatile__("membar #Sync\n\t"
171 "lduha [%1] %2, %0\n\t"
172 "membar #Sync"
173 : "=r" (_unused)
174 : "r" ((u16 *) config_space),
175 "i" (ASI_PHYS_BYPASS_EC_E_L)
176 : "memory");
177
178 sabre_read(sync_reg);
179}
180
181#define SABRE_IMAP_A_SLOT0 0x0c00UL
182#define SABRE_IMAP_B_SLOT0 0x0c20UL
183#define SABRE_ICLR_A_SLOT0 0x1400UL
184#define SABRE_ICLR_B_SLOT0 0x1480UL
185#define SABRE_ICLR_SCSI 0x1800UL
186#define SABRE_ICLR_ETH 0x1808UL
187#define SABRE_ICLR_BPP 0x1810UL
188#define SABRE_ICLR_AU_REC 0x1818UL
189#define SABRE_ICLR_AU_PLAY 0x1820UL
190#define SABRE_ICLR_PFAIL 0x1828UL
191#define SABRE_ICLR_KMS 0x1830UL
192#define SABRE_ICLR_FLPY 0x1838UL
193#define SABRE_ICLR_SHW 0x1840UL
194#define SABRE_ICLR_KBD 0x1848UL
195#define SABRE_ICLR_MS 0x1850UL
196#define SABRE_ICLR_SER 0x1858UL
197#define SABRE_ICLR_UE 0x1870UL
198#define SABRE_ICLR_CE 0x1878UL
199#define SABRE_ICLR_PCIERR 0x1880UL
200
201static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
202{
203 unsigned int bus = (ino & 0x10) >> 4;
204 unsigned int slot = (ino & 0x0c) >> 2;
205
206 if (bus == 0)
207 return SABRE_IMAP_A_SLOT0 + (slot * 8);
208 else
209 return SABRE_IMAP_B_SLOT0 + (slot * 8);
210}
211
212#define SABRE_OBIO_IMAP_BASE 0x1000UL
213#define SABRE_ONBOARD_IRQ_BASE 0x20
214#define sabre_onboard_imap_offset(__ino) \
215 (SABRE_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
216
217#define sabre_iclr_offset(ino) \
218 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
219 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
220
221static int sabre_device_needs_wsync(struct device_node *dp)
222{
223 struct device_node *parent = dp->parent;
224 const char *parent_model, *parent_compat;
225
226 /* This traversal up towards the root is meant to
227 * handle two cases:
228 *
229 * 1) non-PCI bus sitting under PCI, such as 'ebus'
230 * 2) the PCI controller interrupts themselves, which
231 * will use the sabre_irq_build but do not need
232 * the DMA synchronization handling
233 */
234 while (parent) {
235 if (!strcmp(parent->type, "pci"))
236 break;
237 parent = parent->parent;
238 }
239
240 if (!parent)
241 return 0;
242
243 parent_model = of_get_property(parent,
244 "model", NULL);
245 if (parent_model &&
246 (!strcmp(parent_model, "SUNW,sabre") ||
247 !strcmp(parent_model, "SUNW,simba")))
248 return 0;
249
250 parent_compat = of_get_property(parent,
251 "compatible", NULL);
252 if (parent_compat &&
253 (!strcmp(parent_compat, "pci108e,a000") ||
254 !strcmp(parent_compat, "pci108e,a001")))
255 return 0;
256
257 return 1;
258}
259
260static unsigned int sabre_irq_build(struct device_node *dp,
261 unsigned int ino,
262 void *_data)
263{
264 struct sabre_irq_data *irq_data = _data;
265 unsigned long controller_regs = irq_data->controller_regs;
266 const struct linux_prom_pci_registers *regs;
267 unsigned long imap, iclr;
268 unsigned long imap_off, iclr_off;
269 int inofixup = 0;
270 int virt_irq;
271
272 ino &= 0x3f;
273 if (ino < SABRE_ONBOARD_IRQ_BASE) {
274 /* PCI slot */
275 imap_off = sabre_pcislot_imap_offset(ino);
276 } else {
277 /* onboard device */
278 imap_off = sabre_onboard_imap_offset(ino);
279 }
280
281 /* Now build the IRQ bucket. */
282 imap = controller_regs + imap_off;
283
284 iclr_off = sabre_iclr_offset(ino);
285 iclr = controller_regs + iclr_off;
286
287 if ((ino & 0x20) == 0)
288 inofixup = ino & 0x03;
289
290 virt_irq = build_irq(inofixup, iclr, imap);
291
292 /* If the parent device is a PCI<->PCI bridge other than
293 * APB, we have to install a pre-handler to ensure that
294 * all pending DMA is drained before the interrupt handler
295 * is run.
296 */
297 regs = of_get_property(dp, "reg", NULL);
298 if (regs && sabre_device_needs_wsync(dp)) {
299 irq_install_pre_handler(virt_irq,
300 sabre_wsync_handler,
301 (void *) (long) regs->phys_hi,
302 (void *) irq_data);
303 }
304
305 return virt_irq;
306}
307
308static void __init sabre_irq_trans_init(struct device_node *dp)
309{
310 const struct linux_prom64_registers *regs;
311 struct sabre_irq_data *irq_data;
312 const u32 *busrange;
313
314 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
315 dp->irq_trans->irq_build = sabre_irq_build;
316
317 irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
318
319 regs = of_get_property(dp, "reg", NULL);
320 irq_data->controller_regs = regs[0].phys_addr;
321
322 busrange = of_get_property(dp, "bus-range", NULL);
323 irq_data->pci_first_busno = busrange[0];
324
325 dp->irq_trans->data = irq_data;
326}
327
328/* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
329 * imap/iclr registers are per-PBM.
330 */
331#define SCHIZO_IMAP_BASE 0x1000UL
332#define SCHIZO_ICLR_BASE 0x1400UL
333
334static unsigned long schizo_imap_offset(unsigned long ino)
335{
336 return SCHIZO_IMAP_BASE + (ino * 8UL);
337}
338
339static unsigned long schizo_iclr_offset(unsigned long ino)
340{
341 return SCHIZO_ICLR_BASE + (ino * 8UL);
342}
343
344static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
345 unsigned int ino)
346{
347
348 return pbm_regs + schizo_iclr_offset(ino);
349}
350
351static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
352 unsigned int ino)
353{
354 return pbm_regs + schizo_imap_offset(ino);
355}
356
357#define schizo_read(__reg) \
358({ u64 __ret; \
359 __asm__ __volatile__("ldxa [%1] %2, %0" \
360 : "=r" (__ret) \
361 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
362 : "memory"); \
363 __ret; \
364})
365#define schizo_write(__reg, __val) \
366 __asm__ __volatile__("stxa %0, [%1] %2" \
367 : /* no outputs */ \
368 : "r" (__val), "r" (__reg), \
369 "i" (ASI_PHYS_BYPASS_EC_E) \
370 : "memory")
371
372static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
373{
374 unsigned long sync_reg = (unsigned long) _arg2;
375 u64 mask = 1UL << (ino & IMAP_INO);
376 u64 val;
377 int limit;
378
379 schizo_write(sync_reg, mask);
380
381 limit = 100000;
382 val = 0;
383 while (--limit) {
384 val = schizo_read(sync_reg);
385 if (!(val & mask))
386 break;
387 }
388 if (limit <= 0) {
389 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
390 val, mask);
391 }
392
393 if (_arg1) {
394 static unsigned char cacheline[64]
395 __attribute__ ((aligned (64)));
396
397 __asm__ __volatile__("rd %%fprs, %0\n\t"
398 "or %0, %4, %1\n\t"
399 "wr %1, 0x0, %%fprs\n\t"
400 "stda %%f0, [%5] %6\n\t"
401 "wr %0, 0x0, %%fprs\n\t"
402 "membar #Sync"
403 : "=&r" (mask), "=&r" (val)
404 : "0" (mask), "1" (val),
405 "i" (FPRS_FEF), "r" (&cacheline[0]),
406 "i" (ASI_BLK_COMMIT_P));
407 }
408}
409
410struct schizo_irq_data {
411 unsigned long pbm_regs;
412 unsigned long sync_reg;
413 u32 portid;
414 int chip_version;
415};
416
417static unsigned int schizo_irq_build(struct device_node *dp,
418 unsigned int ino,
419 void *_data)
420{
421 struct schizo_irq_data *irq_data = _data;
422 unsigned long pbm_regs = irq_data->pbm_regs;
423 unsigned long imap, iclr;
424 int ign_fixup;
425 int virt_irq;
426 int is_tomatillo;
427
428 ino &= 0x3f;
429
430 /* Now build the IRQ bucket. */
431 imap = schizo_ino_to_imap(pbm_regs, ino);
432 iclr = schizo_ino_to_iclr(pbm_regs, ino);
433
434 /* On Schizo, no inofixup occurs. This is because each
435 * INO has it's own IMAP register. On Psycho and Sabre
436 * there is only one IMAP register for each PCI slot even
437 * though four different INOs can be generated by each
438 * PCI slot.
439 *
440 * But, for JBUS variants (essentially, Tomatillo), we have
441 * to fixup the lowest bit of the interrupt group number.
442 */
443 ign_fixup = 0;
444
445 is_tomatillo = (irq_data->sync_reg != 0UL);
446
447 if (is_tomatillo) {
448 if (irq_data->portid & 1)
449 ign_fixup = (1 << 6);
450 }
451
452 virt_irq = build_irq(ign_fixup, iclr, imap);
453
454 if (is_tomatillo) {
455 irq_install_pre_handler(virt_irq,
456 tomatillo_wsync_handler,
457 ((irq_data->chip_version <= 4) ?
458 (void *) 1 : (void *) 0),
459 (void *) irq_data->sync_reg);
460 }
461
462 return virt_irq;
463}
464
465static void __init __schizo_irq_trans_init(struct device_node *dp,
466 int is_tomatillo)
467{
468 const struct linux_prom64_registers *regs;
469 struct schizo_irq_data *irq_data;
470
471 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
472 dp->irq_trans->irq_build = schizo_irq_build;
473
474 irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
475
476 regs = of_get_property(dp, "reg", NULL);
477 dp->irq_trans->data = irq_data;
478
479 irq_data->pbm_regs = regs[0].phys_addr;
480 if (is_tomatillo)
481 irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
482 else
483 irq_data->sync_reg = 0UL;
484 irq_data->portid = of_getintprop_default(dp, "portid", 0);
485 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
486}
487
488static void __init schizo_irq_trans_init(struct device_node *dp)
489{
490 __schizo_irq_trans_init(dp, 0);
491}
492
493static void __init tomatillo_irq_trans_init(struct device_node *dp)
494{
495 __schizo_irq_trans_init(dp, 1);
496}
497
498static unsigned int pci_sun4v_irq_build(struct device_node *dp,
499 unsigned int devino,
500 void *_data)
501{
502 u32 devhandle = (u32) (unsigned long) _data;
503
504 return sun4v_build_irq(devhandle, devino);
505}
506
507static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
508{
509 const struct linux_prom64_registers *regs;
510
511 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
512 dp->irq_trans->irq_build = pci_sun4v_irq_build;
513
514 regs = of_get_property(dp, "reg", NULL);
515 dp->irq_trans->data = (void *) (unsigned long)
516 ((regs->phys_addr >> 32UL) & 0x0fffffff);
517}
518
519struct fire_irq_data {
520 unsigned long pbm_regs;
521 u32 portid;
522};
523
524#define FIRE_IMAP_BASE 0x001000
525#define FIRE_ICLR_BASE 0x001400
526
527static unsigned long fire_imap_offset(unsigned long ino)
528{
529 return FIRE_IMAP_BASE + (ino * 8UL);
530}
531
532static unsigned long fire_iclr_offset(unsigned long ino)
533{
534 return FIRE_ICLR_BASE + (ino * 8UL);
535}
536
537static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
538 unsigned int ino)
539{
540 return pbm_regs + fire_iclr_offset(ino);
541}
542
543static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
544 unsigned int ino)
545{
546 return pbm_regs + fire_imap_offset(ino);
547}
548
549static unsigned int fire_irq_build(struct device_node *dp,
550 unsigned int ino,
551 void *_data)
552{
553 struct fire_irq_data *irq_data = _data;
554 unsigned long pbm_regs = irq_data->pbm_regs;
555 unsigned long imap, iclr;
556 unsigned long int_ctrlr;
557
558 ino &= 0x3f;
559
560 /* Now build the IRQ bucket. */
561 imap = fire_ino_to_imap(pbm_regs, ino);
562 iclr = fire_ino_to_iclr(pbm_regs, ino);
563
564 /* Set the interrupt controller number. */
565 int_ctrlr = 1 << 6;
566 upa_writeq(int_ctrlr, imap);
567
568 /* The interrupt map registers do not have an INO field
569 * like other chips do. They return zero in the INO
570 * field, and the interrupt controller number is controlled
571 * in bits 6 to 9. So in order for build_irq() to get
572 * the INO right we pass it in as part of the fixup
573 * which will get added to the map register zero value
574 * read by build_irq().
575 */
576 ino |= (irq_data->portid << 6);
577 ino -= int_ctrlr;
578 return build_irq(ino, iclr, imap);
579}
580
581static void __init fire_irq_trans_init(struct device_node *dp)
582{
583 const struct linux_prom64_registers *regs;
584 struct fire_irq_data *irq_data;
585
586 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
587 dp->irq_trans->irq_build = fire_irq_build;
588
589 irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
590
591 regs = of_get_property(dp, "reg", NULL);
592 dp->irq_trans->data = irq_data;
593
594 irq_data->pbm_regs = regs[0].phys_addr;
595 irq_data->portid = of_getintprop_default(dp, "portid", 0);
596}
597#endif /* CONFIG_PCI */
598
599#ifdef CONFIG_SBUS
600/* INO number to IMAP register offset for SYSIO external IRQ's.
601 * This should conform to both Sunfire/Wildfire server and Fusion
602 * desktop designs.
603 */
604#define SYSIO_IMAP_SLOT0 0x2c00UL
605#define SYSIO_IMAP_SLOT1 0x2c08UL
606#define SYSIO_IMAP_SLOT2 0x2c10UL
607#define SYSIO_IMAP_SLOT3 0x2c18UL
608#define SYSIO_IMAP_SCSI 0x3000UL
609#define SYSIO_IMAP_ETH 0x3008UL
610#define SYSIO_IMAP_BPP 0x3010UL
611#define SYSIO_IMAP_AUDIO 0x3018UL
612#define SYSIO_IMAP_PFAIL 0x3020UL
613#define SYSIO_IMAP_KMS 0x3028UL
614#define SYSIO_IMAP_FLPY 0x3030UL
615#define SYSIO_IMAP_SHW 0x3038UL
616#define SYSIO_IMAP_KBD 0x3040UL
617#define SYSIO_IMAP_MS 0x3048UL
618#define SYSIO_IMAP_SER 0x3050UL
619#define SYSIO_IMAP_TIM0 0x3060UL
620#define SYSIO_IMAP_TIM1 0x3068UL
621#define SYSIO_IMAP_UE 0x3070UL
622#define SYSIO_IMAP_CE 0x3078UL
623#define SYSIO_IMAP_SBERR 0x3080UL
624#define SYSIO_IMAP_PMGMT 0x3088UL
625#define SYSIO_IMAP_GFX 0x3090UL
626#define SYSIO_IMAP_EUPA 0x3098UL
627
628#define bogon ((unsigned long) -1)
629static unsigned long sysio_irq_offsets[] = {
630 /* SBUS Slot 0 --> 3, level 1 --> 7 */
631 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
632 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
633 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
634 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
635 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
636 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
637 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
638 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
639
640 /* Onboard devices (not relevant/used on SunFire). */
641 SYSIO_IMAP_SCSI,
642 SYSIO_IMAP_ETH,
643 SYSIO_IMAP_BPP,
644 bogon,
645 SYSIO_IMAP_AUDIO,
646 SYSIO_IMAP_PFAIL,
647 bogon,
648 bogon,
649 SYSIO_IMAP_KMS,
650 SYSIO_IMAP_FLPY,
651 SYSIO_IMAP_SHW,
652 SYSIO_IMAP_KBD,
653 SYSIO_IMAP_MS,
654 SYSIO_IMAP_SER,
655 bogon,
656 bogon,
657 SYSIO_IMAP_TIM0,
658 SYSIO_IMAP_TIM1,
659 bogon,
660 bogon,
661 SYSIO_IMAP_UE,
662 SYSIO_IMAP_CE,
663 SYSIO_IMAP_SBERR,
664 SYSIO_IMAP_PMGMT,
665 SYSIO_IMAP_GFX,
666 SYSIO_IMAP_EUPA,
667};
668
669#undef bogon
670
671#define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
672
673/* Convert Interrupt Mapping register pointer to associated
674 * Interrupt Clear register pointer, SYSIO specific version.
675 */
676#define SYSIO_ICLR_UNUSED0 0x3400UL
677#define SYSIO_ICLR_SLOT0 0x3408UL
678#define SYSIO_ICLR_SLOT1 0x3448UL
679#define SYSIO_ICLR_SLOT2 0x3488UL
680#define SYSIO_ICLR_SLOT3 0x34c8UL
681static unsigned long sysio_imap_to_iclr(unsigned long imap)
682{
683 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
684 return imap + diff;
685}
686
687static unsigned int sbus_of_build_irq(struct device_node *dp,
688 unsigned int ino,
689 void *_data)
690{
691 unsigned long reg_base = (unsigned long) _data;
692 const struct linux_prom_registers *regs;
693 unsigned long imap, iclr;
694 int sbus_slot = 0;
695 int sbus_level = 0;
696
697 ino &= 0x3f;
698
699 regs = of_get_property(dp, "reg", NULL);
700 if (regs)
701 sbus_slot = regs->which_io;
702
703 if (ino < 0x20)
704 ino += (sbus_slot * 8);
705
706 imap = sysio_irq_offsets[ino];
707 if (imap == ((unsigned long)-1)) {
708 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
709 ino);
710 prom_halt();
711 }
712 imap += reg_base;
713
714 /* SYSIO inconsistency. For external SLOTS, we have to select
715 * the right ICLR register based upon the lower SBUS irq level
716 * bits.
717 */
718 if (ino >= 0x20) {
719 iclr = sysio_imap_to_iclr(imap);
720 } else {
721 sbus_level = ino & 0x7;
722
723 switch(sbus_slot) {
724 case 0:
725 iclr = reg_base + SYSIO_ICLR_SLOT0;
726 break;
727 case 1:
728 iclr = reg_base + SYSIO_ICLR_SLOT1;
729 break;
730 case 2:
731 iclr = reg_base + SYSIO_ICLR_SLOT2;
732 break;
733 default:
734 case 3:
735 iclr = reg_base + SYSIO_ICLR_SLOT3;
736 break;
737 };
738
739 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
740 }
741 return build_irq(sbus_level, iclr, imap);
742}
743
744static void __init sbus_irq_trans_init(struct device_node *dp)
745{
746 const struct linux_prom64_registers *regs;
747
748 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
749 dp->irq_trans->irq_build = sbus_of_build_irq;
750
751 regs = of_get_property(dp, "reg", NULL);
752 dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
753}
754#endif /* CONFIG_SBUS */
755
756
757static unsigned int central_build_irq(struct device_node *dp,
758 unsigned int ino,
759 void *_data)
760{
761 struct device_node *central_dp = _data;
762 struct of_device *central_op = of_find_device_by_node(central_dp);
763 struct resource *res;
764 unsigned long imap, iclr;
765 u32 tmp;
766
767 if (!strcmp(dp->name, "eeprom")) {
768 res = &central_op->resource[5];
769 } else if (!strcmp(dp->name, "zs")) {
770 res = &central_op->resource[4];
771 } else if (!strcmp(dp->name, "clock-board")) {
772 res = &central_op->resource[3];
773 } else {
774 return ino;
775 }
776
777 imap = res->start + 0x00UL;
778 iclr = res->start + 0x10UL;
779
780 /* Set the INO state to idle, and disable. */
781 upa_writel(0, iclr);
782 upa_readl(iclr);
783
784 tmp = upa_readl(imap);
785 tmp &= ~0x80000000;
786 upa_writel(tmp, imap);
787
788 return build_irq(0, iclr, imap);
789}
790
791static void __init central_irq_trans_init(struct device_node *dp)
792{
793 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
794 dp->irq_trans->irq_build = central_build_irq;
795
796 dp->irq_trans->data = dp;
797}
798
799struct irq_trans {
800 const char *name;
801 void (*init)(struct device_node *);
802};
803
804#ifdef CONFIG_PCI
805static struct irq_trans __initdata pci_irq_trans_table[] = {
806 { "SUNW,sabre", sabre_irq_trans_init },
807 { "pci108e,a000", sabre_irq_trans_init },
808 { "pci108e,a001", sabre_irq_trans_init },
809 { "SUNW,psycho", psycho_irq_trans_init },
810 { "pci108e,8000", psycho_irq_trans_init },
811 { "SUNW,schizo", schizo_irq_trans_init },
812 { "pci108e,8001", schizo_irq_trans_init },
813 { "SUNW,schizo+", schizo_irq_trans_init },
814 { "pci108e,8002", schizo_irq_trans_init },
815 { "SUNW,tomatillo", tomatillo_irq_trans_init },
816 { "pci108e,a801", tomatillo_irq_trans_init },
817 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
818 { "pciex108e,80f0", fire_irq_trans_init },
819};
820#endif
821
822static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
823 unsigned int devino,
824 void *_data)
825{
826 u32 devhandle = (u32) (unsigned long) _data;
827
828 return sun4v_build_irq(devhandle, devino);
829}
830
831static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
832{
833 const struct linux_prom64_registers *regs;
834
835 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
836 dp->irq_trans->irq_build = sun4v_vdev_irq_build;
837
838 regs = of_get_property(dp, "reg", NULL);
839 dp->irq_trans->data = (void *) (unsigned long)
840 ((regs->phys_addr >> 32UL) & 0x0fffffff);
841}
842
843static void __init irq_trans_init(struct device_node *dp)
844{
845#ifdef CONFIG_PCI
846 const char *model;
847 int i;
848#endif
849
850#ifdef CONFIG_PCI
851 model = of_get_property(dp, "model", NULL);
852 if (!model)
853 model = of_get_property(dp, "compatible", NULL);
854 if (model) {
855 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
856 struct irq_trans *t = &pci_irq_trans_table[i];
857
858 if (!strcmp(model, t->name)) {
859 t->init(dp);
860 return;
861 }
862 }
863 }
864#endif
865#ifdef CONFIG_SBUS
866 if (!strcmp(dp->name, "sbus") ||
867 !strcmp(dp->name, "sbi")) {
868 sbus_irq_trans_init(dp);
869 return;
870 }
871#endif
872 if (!strcmp(dp->name, "fhc") &&
873 !strcmp(dp->parent->name, "central")) {
874 central_irq_trans_init(dp);
875 return;
876 }
877 if (!strcmp(dp->name, "virtual-devices") ||
878 !strcmp(dp->name, "niu")) {
879 sun4v_vdev_irq_trans_init(dp);
880 return;
881 }
882}
883
884static int is_root_node(const struct device_node *dp) 54static int is_root_node(const struct device_node *dp)
885{ 55{
886 if (!dp) 56 if (!dp)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 17:49:11 -0500