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authorSam Ravnborg <sam@ravnborg.org>2008-12-03 06:11:52 -0500
committerDavid S. Miller <davem@davemloft.net>2008-12-04 12:17:21 -0500
commita88b5ba8bd8ac18aad65ee6c6a254e2e74876db3 (patch)
treeeb3d0ffaf53c3f7ec6083752c2097cecd1cb892a /arch/sparc/kernel/pci_impl.h
parentd670bd4f803c8b646acd20f3ba21e65458293faf (diff)
sparc,sparc64: unify kernel/
o Move all files from sparc64/kernel/ to sparc/kernel - rename as appropriate o Update sparc/Makefile to the changes o Update sparc/kernel/Makefile to include the sparc64 files NOTE: This commit changes link order on sparc64! Link order had to change for either of sparc32 and sparc64. And assuming sparc64 see more testing than sparc32 change link order on sparc64 where issues will be caught faster. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel/pci_impl.h')
-rw-r--r--arch/sparc/kernel/pci_impl.h185
1 files changed, 185 insertions, 0 deletions
diff --git a/arch/sparc/kernel/pci_impl.h b/arch/sparc/kernel/pci_impl.h
new file mode 100644
index 000000000000..03186824327e
--- /dev/null
+++ b/arch/sparc/kernel/pci_impl.h
@@ -0,0 +1,185 @@
1/* pci_impl.h: Helper definitions for PCI controller support.
2 *
3 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#ifndef PCI_IMPL_H
7#define PCI_IMPL_H
8
9#include <linux/types.h>
10#include <linux/spinlock.h>
11#include <linux/pci.h>
12#include <linux/msi.h>
13#include <linux/of_device.h>
14#include <asm/io.h>
15#include <asm/prom.h>
16#include <asm/iommu.h>
17
18/* The abstraction used here is that there are PCI controllers,
19 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
20 * underneath. Each PCI bus module uses an IOMMU (shared by both
21 * PBMs of a controller, or per-PBM), and if a streaming buffer
22 * is present, each PCI bus module has it's own. (ie. the IOMMU
23 * might be shared between PBMs, the STC is never shared)
24 * Furthermore, each PCI bus module controls it's own autonomous
25 * PCI bus.
26 */
27
28#define PCI_STC_FLUSHFLAG_INIT(STC) \
29 (*((STC)->strbuf_flushflag) = 0UL)
30#define PCI_STC_FLUSHFLAG_SET(STC) \
31 (*((STC)->strbuf_flushflag) != 0UL)
32
33#ifdef CONFIG_PCI_MSI
34struct pci_pbm_info;
35struct sparc64_msiq_ops {
36 int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
37 unsigned long *head);
38 int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid,
39 unsigned long *head, unsigned long *msi);
40 int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
41 unsigned long head);
42 int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid,
43 unsigned long msi, int is_msi64);
44 int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi);
45 int (*msiq_alloc)(struct pci_pbm_info *pbm);
46 void (*msiq_free)(struct pci_pbm_info *pbm);
47 int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid,
48 unsigned long devino);
49};
50
51extern void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
52 const struct sparc64_msiq_ops *ops);
53
54struct sparc64_msiq_cookie {
55 struct pci_pbm_info *pbm;
56 unsigned long msiqid;
57};
58#endif
59
60struct pci_pbm_info {
61 struct pci_pbm_info *next;
62 struct pci_pbm_info *sibling;
63 int index;
64
65 /* Physical address base of controller registers. */
66 unsigned long controller_regs;
67
68 /* Physical address base of PBM registers. */
69 unsigned long pbm_regs;
70
71 /* Physical address of DMA sync register, if any. */
72 unsigned long sync_reg;
73
74 /* Opaque 32-bit system bus Port ID. */
75 u32 portid;
76
77 /* Opaque 32-bit handle used for hypervisor calls. */
78 u32 devhandle;
79
80 /* Chipset version information. */
81 int chip_type;
82#define PBM_CHIP_TYPE_SABRE 1
83#define PBM_CHIP_TYPE_PSYCHO 2
84#define PBM_CHIP_TYPE_SCHIZO 3
85#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
86#define PBM_CHIP_TYPE_TOMATILLO 5
87 int chip_version;
88 int chip_revision;
89
90 /* Name used for top-level resources. */
91 char *name;
92
93 /* OBP specific information. */
94 struct of_device *op;
95 u64 ino_bitmap;
96
97 /* PBM I/O and Memory space resources. */
98 struct resource io_space;
99 struct resource mem_space;
100
101 /* Base of PCI Config space, can be per-PBM or shared. */
102 unsigned long config_space;
103
104 /* This will be 12 on PCI-E controllers, 8 elsewhere. */
105 unsigned long config_space_reg_bits;
106
107 unsigned long pci_afsr;
108 unsigned long pci_afar;
109 unsigned long pci_csr;
110
111 /* State of 66MHz capabilities on this PBM. */
112 int is_66mhz_capable;
113 int all_devs_66mhz;
114
115#ifdef CONFIG_PCI_MSI
116 /* MSI info. */
117 u32 msiq_num;
118 u32 msiq_ent_count;
119 u32 msiq_first;
120 u32 msiq_first_devino;
121 u32 msiq_rotor;
122 struct sparc64_msiq_cookie *msiq_irq_cookies;
123 u32 msi_num;
124 u32 msi_first;
125 u32 msi_data_mask;
126 u32 msix_data_width;
127 u64 msi32_start;
128 u64 msi64_start;
129 u32 msi32_len;
130 u32 msi64_len;
131 void *msi_queues;
132 unsigned long *msi_bitmap;
133 unsigned int *msi_irq_table;
134 int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
135 struct msi_desc *entry);
136 void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
137 const struct sparc64_msiq_ops *msi_ops;
138#endif /* !(CONFIG_PCI_MSI) */
139
140 /* This PBM's streaming buffer. */
141 struct strbuf stc;
142
143 /* IOMMU state, potentially shared by both PBM segments. */
144 struct iommu *iommu;
145
146 /* Now things for the actual PCI bus probes. */
147 unsigned int pci_first_busno;
148 unsigned int pci_last_busno;
149 struct pci_bus *pci_bus;
150 struct pci_ops *pci_ops;
151
152 int numa_node;
153};
154
155extern struct pci_pbm_info *pci_pbm_root;
156
157extern int pci_num_pbms;
158
159/* PCI bus scanning and fixup support. */
160extern void pci_get_pbm_props(struct pci_pbm_info *pbm);
161extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
162 struct device *parent);
163extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
164
165/* Error reporting support. */
166extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
167extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
168extern void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
169
170/* Configuration space access. */
171extern void pci_config_read8(u8 *addr, u8 *ret);
172extern void pci_config_read16(u16 *addr, u16 *ret);
173extern void pci_config_read32(u32 *addr, u32 *ret);
174extern void pci_config_write8(u8 *addr, u8 val);
175extern void pci_config_write16(u16 *addr, u16 val);
176extern void pci_config_write32(u32 *addr, u32 val);
177
178extern struct pci_ops sun4u_pci_ops;
179extern struct pci_ops sun4v_pci_ops;
180
181extern volatile int pci_poke_in_progress;
182extern volatile int pci_poke_cpu;
183extern volatile int pci_poke_faulted;
184
185#endif /* !(PCI_IMPL_H) */
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