sparc: sun4m SMP: fix wrong shift instruction in IPI handler

This shift instruction appears to be shifting in the wrong direction.
Without this change, my SparcStation-20MP hangs just after bringing up
the second CPU:

Entering SMP Mode...
Starting CPU 2 at f02b4e90
Brought up 2 CPUs
Total of 2 processors activated (99.52 BogoMIPS).
   *** stuck ***

Signed-off-by: Will Simoneau <simoneau@ele.uri.edu>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index 9fe08a1ea6c6..f445e98463e6 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -293,7 +293,7 @@ maybe_smp4m_msg:
         WRITE_PAUSE
         wr      %l4, PSR_ET, %psr
         WRITE_PAUSE
-        sll     %o3, 28, %o2            ! shift for simpler checks below
+        srl     %o3, 28, %o2            ! shift for simpler checks below
 maybe_smp4m_msg_check_single:
         andcc   %o2, 0x1, %g0
         beq,a   maybe_smp4m_msg_check_mask