diff options
author | David S. Miller <davem@davemloft.net> | 2009-01-22 02:16:40 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-01-28 20:27:14 -0500 |
commit | c3cf5e8cc56d272f828a66610bb78bbb727b2ce1 (patch) | |
tree | ad3a585af35f53b12ab0ea25a929fb2d64c74b73 /arch/sparc/kernel/cpu.c | |
parent | 3eb8057bbafc64dbf09d5c18513aa80c1b7f2fcb (diff) |
sparc: Probe PMU type and record in sparc_pmu_type.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel/cpu.c')
-rw-r--r-- | arch/sparc/kernel/cpu.c | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c index 32d32b4824f5..d85c3dc4953a 100644 --- a/arch/sparc/kernel/cpu.c +++ b/arch/sparc/kernel/cpu.c | |||
@@ -26,6 +26,7 @@ EXPORT_PER_CPU_SYMBOL(__cpu_data); | |||
26 | struct cpu_info { | 26 | struct cpu_info { |
27 | int psr_vers; | 27 | int psr_vers; |
28 | const char *name; | 28 | const char *name; |
29 | const char *pmu_name; | ||
29 | }; | 30 | }; |
30 | 31 | ||
31 | struct fpu_info { | 32 | struct fpu_info { |
@@ -45,6 +46,9 @@ struct manufacturer_info { | |||
45 | #define CPU(ver, _name) \ | 46 | #define CPU(ver, _name) \ |
46 | { .psr_vers = ver, .name = _name } | 47 | { .psr_vers = ver, .name = _name } |
47 | 48 | ||
49 | #define CPU_PMU(ver, _name, _pmu_name) \ | ||
50 | { .psr_vers = ver, .name = _name, .pmu_name = _pmu_name } | ||
51 | |||
48 | #define FPU(ver, _name) \ | 52 | #define FPU(ver, _name) \ |
49 | { .fp_vers = ver, .name = _name } | 53 | { .fp_vers = ver, .name = _name } |
50 | 54 | ||
@@ -183,10 +187,10 @@ static const struct manufacturer_info __initconst manufacturer_info[] = { | |||
183 | },{ | 187 | },{ |
184 | 0x17, | 188 | 0x17, |
185 | .cpu_info = { | 189 | .cpu_info = { |
186 | CPU(0x10, "TI UltraSparc I (SpitFire)"), | 190 | CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"), |
187 | CPU(0x11, "TI UltraSparc II (BlackBird)"), | 191 | CPU_PMU(0x11, "TI UltraSparc II (BlackBird)", "ultra12"), |
188 | CPU(0x12, "TI UltraSparc IIi (Sabre)"), | 192 | CPU_PMU(0x12, "TI UltraSparc IIi (Sabre)", "ultra12"), |
189 | CPU(0x13, "TI UltraSparc IIe (Hummingbird)"), | 193 | CPU_PMU(0x13, "TI UltraSparc IIe (Hummingbird)", "ultra12"), |
190 | CPU(-1, NULL) | 194 | CPU(-1, NULL) |
191 | }, | 195 | }, |
192 | .fpu_info = { | 196 | .fpu_info = { |
@@ -199,7 +203,7 @@ static const struct manufacturer_info __initconst manufacturer_info[] = { | |||
199 | },{ | 203 | },{ |
200 | 0x22, | 204 | 0x22, |
201 | .cpu_info = { | 205 | .cpu_info = { |
202 | CPU(0x10, "TI UltraSparc I (SpitFire)"), | 206 | CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"), |
203 | CPU(-1, NULL) | 207 | CPU(-1, NULL) |
204 | }, | 208 | }, |
205 | .fpu_info = { | 209 | .fpu_info = { |
@@ -209,12 +213,12 @@ static const struct manufacturer_info __initconst manufacturer_info[] = { | |||
209 | },{ | 213 | },{ |
210 | 0x3e, | 214 | 0x3e, |
211 | .cpu_info = { | 215 | .cpu_info = { |
212 | CPU(0x14, "TI UltraSparc III (Cheetah)"), | 216 | CPU_PMU(0x14, "TI UltraSparc III (Cheetah)", "ultra3"), |
213 | CPU(0x15, "TI UltraSparc III+ (Cheetah+)"), | 217 | CPU_PMU(0x15, "TI UltraSparc III+ (Cheetah+)", "ultra3+"), |
214 | CPU(0x16, "TI UltraSparc IIIi (Jalapeno)"), | 218 | CPU_PMU(0x16, "TI UltraSparc IIIi (Jalapeno)", "ultra3i"), |
215 | CPU(0x18, "TI UltraSparc IV (Jaguar)"), | 219 | CPU_PMU(0x18, "TI UltraSparc IV (Jaguar)", "ultra3+"), |
216 | CPU(0x19, "TI UltraSparc IV+ (Panther)"), | 220 | CPU_PMU(0x19, "TI UltraSparc IV+ (Panther)", "ultra4+"), |
217 | CPU(0x22, "TI UltraSparc IIIi+ (Serrano)"), | 221 | CPU_PMU(0x22, "TI UltraSparc IIIi+ (Serrano)", "ultra3i"), |
218 | CPU(-1, NULL) | 222 | CPU(-1, NULL) |
219 | }, | 223 | }, |
220 | .fpu_info = { | 224 | .fpu_info = { |
@@ -234,6 +238,7 @@ static const struct manufacturer_info __initconst manufacturer_info[] = { | |||
234 | 238 | ||
235 | const char *sparc_cpu_type; | 239 | const char *sparc_cpu_type; |
236 | const char *sparc_fpu_type; | 240 | const char *sparc_fpu_type; |
241 | const char *sparc_pmu_type; | ||
237 | 242 | ||
238 | unsigned int fsr_storage; | 243 | unsigned int fsr_storage; |
239 | 244 | ||
@@ -244,6 +249,7 @@ static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers) | |||
244 | 249 | ||
245 | sparc_cpu_type = NULL; | 250 | sparc_cpu_type = NULL; |
246 | sparc_fpu_type = NULL; | 251 | sparc_fpu_type = NULL; |
252 | sparc_pmu_type = NULL; | ||
247 | manuf = NULL; | 253 | manuf = NULL; |
248 | 254 | ||
249 | for (i = 0; i < ARRAY_SIZE(manufacturer_info); i++) | 255 | for (i = 0; i < ARRAY_SIZE(manufacturer_info); i++) |
@@ -263,6 +269,7 @@ static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers) | |||
263 | { | 269 | { |
264 | if (cpu->psr_vers == psr_vers) { | 270 | if (cpu->psr_vers == psr_vers) { |
265 | sparc_cpu_type = cpu->name; | 271 | sparc_cpu_type = cpu->name; |
272 | sparc_pmu_type = cpu->pmu_name; | ||
266 | sparc_fpu_type = "No FPU"; | 273 | sparc_fpu_type = "No FPU"; |
267 | break; | 274 | break; |
268 | } | 275 | } |
@@ -290,6 +297,8 @@ static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers) | |||
290 | psr_impl, fpu_vers); | 297 | psr_impl, fpu_vers); |
291 | sparc_fpu_type = "Unknown FPU"; | 298 | sparc_fpu_type = "Unknown FPU"; |
292 | } | 299 | } |
300 | if (sparc_pmu_type == NULL) | ||
301 | sparc_pmu_type = "Unknown PMU"; | ||
293 | } | 302 | } |
294 | 303 | ||
295 | #ifdef CONFIG_SPARC32 | 304 | #ifdef CONFIG_SPARC32 |
@@ -315,11 +324,13 @@ static void __init sun4v_cpu_probe(void) | |||
315 | case SUN4V_CHIP_NIAGARA1: | 324 | case SUN4V_CHIP_NIAGARA1: |
316 | sparc_cpu_type = "UltraSparc T1 (Niagara)"; | 325 | sparc_cpu_type = "UltraSparc T1 (Niagara)"; |
317 | sparc_fpu_type = "UltraSparc T1 integrated FPU"; | 326 | sparc_fpu_type = "UltraSparc T1 integrated FPU"; |
327 | sparc_pmu_type = "niagara"; | ||
318 | break; | 328 | break; |
319 | 329 | ||
320 | case SUN4V_CHIP_NIAGARA2: | 330 | case SUN4V_CHIP_NIAGARA2: |
321 | sparc_cpu_type = "UltraSparc T2 (Niagara2)"; | 331 | sparc_cpu_type = "UltraSparc T2 (Niagara2)"; |
322 | sparc_fpu_type = "UltraSparc T2 integrated FPU"; | 332 | sparc_fpu_type = "UltraSparc T2 integrated FPU"; |
333 | sparc_pmu_type = "niagara2"; | ||
323 | break; | 334 | break; |
324 | 335 | ||
325 | default: | 336 | default: |