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authorLinus Torvalds <torvalds@linux-foundation.org>2011-04-07 14:14:49 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-04-07 14:14:49 -0400
commit42933bac11e811f02200c944d8562a15f8ec4ff0 (patch)
treefcdd9afe56eb0e746565ddd1f92f22d36678b843 /arch/sparc/include/asm
parent2b9accbee563f535046ff2cd382d0acaa92e130c (diff)
parent25985edcedea6396277003854657b5f3cb31a628 (diff)
Merge branch 'for-linus2' of git://git.profusion.mobi/users/lucas/linux-2.6
* 'for-linus2' of git://git.profusion.mobi/users/lucas/linux-2.6: Fix common misspellings
Diffstat (limited to 'arch/sparc/include/asm')
-rw-r--r--arch/sparc/include/asm/hypervisor.h20
-rw-r--r--arch/sparc/include/asm/ns87303.h2
-rw-r--r--arch/sparc/include/asm/pcr.h2
-rw-r--r--arch/sparc/include/asm/ptrace.h2
4 files changed, 13 insertions, 13 deletions
diff --git a/arch/sparc/include/asm/hypervisor.h b/arch/sparc/include/asm/hypervisor.h
index bafe5a631b6d..75686409be24 100644
--- a/arch/sparc/include/asm/hypervisor.h
+++ b/arch/sparc/include/asm/hypervisor.h
@@ -654,7 +654,7 @@ extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
654 * ARG3: mmu context 654 * ARG3: mmu context
655 * ARG4: flags (HV_MMU_{IMMU,DMMU}) 655 * ARG4: flags (HV_MMU_{IMMU,DMMU})
656 * RET0: status 656 * RET0: status
657 * ERRORS: EINVAL Invalid virutal address, context, or 657 * ERRORS: EINVAL Invalid virtual address, context, or
658 * flags value 658 * flags value
659 * ENOTSUPPORTED ARG0 or ARG1 is non-zero 659 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
660 * 660 *
@@ -721,7 +721,7 @@ extern void sun4v_mmu_demap_all(void);
721 * ARG2: TTE 721 * ARG2: TTE
722 * ARG3: flags (HV_MMU_{IMMU,DMMU}) 722 * ARG3: flags (HV_MMU_{IMMU,DMMU})
723 * RET0: status 723 * RET0: status
724 * ERRORS: EINVAL Invalid virutal address or flags value 724 * ERRORS: EINVAL Invalid virtual address or flags value
725 * EBADPGSZ Invalid page size value 725 * EBADPGSZ Invalid page size value
726 * ENORADDR Invalid real address in TTE 726 * ENORADDR Invalid real address in TTE
727 * ETOOMANY Too many mappings (max of 8 reached) 727 * ETOOMANY Too many mappings (max of 8 reached)
@@ -800,7 +800,7 @@ extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
800 * ARG1: reserved, must be zero 800 * ARG1: reserved, must be zero
801 * ARG2: flags (HV_MMU_{IMMU,DMMU}) 801 * ARG2: flags (HV_MMU_{IMMU,DMMU})
802 * RET0: status 802 * RET0: status
803 * ERRORS: EINVAL Invalid virutal address or flags value 803 * ERRORS: EINVAL Invalid virtual address or flags value
804 * ENOMAP Specified mapping was not found 804 * ENOMAP Specified mapping was not found
805 * 805 *
806 * Demaps any permanent page mapping (established via 806 * Demaps any permanent page mapping (established via
@@ -1205,7 +1205,7 @@ struct hv_trap_trace_control {
1205 * structure contents. Attempts to do so will result in undefined 1205 * structure contents. Attempts to do so will result in undefined
1206 * behavior for the guest. 1206 * behavior for the guest.
1207 * 1207 *
1208 * Each trap trace buffer entry is layed out as follows: 1208 * Each trap trace buffer entry is laid out as follows:
1209 */ 1209 */
1210#ifndef __ASSEMBLY__ 1210#ifndef __ASSEMBLY__
1211struct hv_trap_trace_entry { 1211struct hv_trap_trace_entry {
@@ -1300,7 +1300,7 @@ struct hv_trap_trace_entry {
1300 * state in RET1. Future systems may define various flags for the 1300 * state in RET1. Future systems may define various flags for the
1301 * enable argument (ARG0), for the moment a guest should pass 1301 * enable argument (ARG0), for the moment a guest should pass
1302 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all 1302 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1303 * tracing - which will ensure future compatability. 1303 * tracing - which will ensure future compatibility.
1304 */ 1304 */
1305#define HV_FAST_TTRACE_ENABLE 0x92 1305#define HV_FAST_TTRACE_ENABLE 0x92
1306 1306
@@ -1880,7 +1880,7 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1880 * pci_device, at pci_config_offset from the beginning of the device's 1880 * pci_device, at pci_config_offset from the beginning of the device's
1881 * configuration space. If there was no error, RET1 is set to zero and 1881 * configuration space. If there was no error, RET1 is set to zero and
1882 * RET2 is set to the data read. Insignificant bits in RET2 are not 1882 * RET2 is set to the data read. Insignificant bits in RET2 are not
1883 * guarenteed to have any specific value and therefore must be ignored. 1883 * guaranteed to have any specific value and therefore must be ignored.
1884 * 1884 *
1885 * The data returned in RET2 is size based byte swapped. 1885 * The data returned in RET2 is size based byte swapped.
1886 * 1886 *
@@ -1941,9 +1941,9 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1941 * and return the actual data read in RET2. The data returned is size based 1941 * and return the actual data read in RET2. The data returned is size based
1942 * byte swapped. 1942 * byte swapped.
1943 * 1943 *
1944 * Non-significant bits in RET2 are not guarenteed to have any specific value 1944 * Non-significant bits in RET2 are not guaranteed to have any specific value
1945 * and therefore must be ignored. If RET1 is returned as non-zero, the data 1945 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1946 * value is not guarenteed to have any specific value and should be ignored. 1946 * value is not guaranteed to have any specific value and should be ignored.
1947 * 1947 *
1948 * The caller must have permission to read from the given devhandle, real 1948 * The caller must have permission to read from the given devhandle, real
1949 * address, which must be an IO address. The argument real address must be a 1949 * address, which must be an IO address. The argument real address must be a
@@ -2456,9 +2456,9 @@ extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
2456 * 2456 *
2457 * As receive queue configuration causes a reset of the queue's head and 2457 * As receive queue configuration causes a reset of the queue's head and
2458 * tail pointers there is no way for a gues to determine how many entries 2458 * tail pointers there is no way for a gues to determine how many entries
2459 * have been received between a preceeding ldc_get_rx_state() API call 2459 * have been received between a preceding ldc_get_rx_state() API call
2460 * and the completion of the configuration operation. It should be noted 2460 * and the completion of the configuration operation. It should be noted
2461 * that datagram delivery is not guarenteed via domain channels anyway, 2461 * that datagram delivery is not guaranteed via domain channels anyway,
2462 * and therefore any higher protocol should be resilient to datagram 2462 * and therefore any higher protocol should be resilient to datagram
2463 * loss if necessary. However, to overcome this specific race potential 2463 * loss if necessary. However, to overcome this specific race potential
2464 * it is recommended, for example, that a higher level protocol be employed 2464 * it is recommended, for example, that a higher level protocol be employed
diff --git a/arch/sparc/include/asm/ns87303.h b/arch/sparc/include/asm/ns87303.h
index 686defe6aaa0..af755483e17d 100644
--- a/arch/sparc/include/asm/ns87303.h
+++ b/arch/sparc/include/asm/ns87303.h
@@ -37,7 +37,7 @@
37/* Power and Test Register (PTR) bits */ 37/* Power and Test Register (PTR) bits */
38#define PTR_LPTB_IRQ7 0x08 38#define PTR_LPTB_IRQ7 0x08
39#define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */ 39#define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
40#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controlls direction */ 40#define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */
41 /* of the parallel port */ 41 /* of the parallel port */
42 42
43/* Function Control Register (FCR) bits */ 43/* Function Control Register (FCR) bits */
diff --git a/arch/sparc/include/asm/pcr.h b/arch/sparc/include/asm/pcr.h
index 843e4faf6a50..288d7beba051 100644
--- a/arch/sparc/include/asm/pcr.h
+++ b/arch/sparc/include/asm/pcr.h
@@ -31,7 +31,7 @@ extern unsigned int picl_shift;
31 31
32/* In order to commonize as much of the implementation as 32/* In order to commonize as much of the implementation as
33 * possible, we use PICH as our counter. Mostly this is 33 * possible, we use PICH as our counter. Mostly this is
34 * to accomodate Niagara-1 which can only count insn cycles 34 * to accommodate Niagara-1 which can only count insn cycles
35 * in PICH. 35 * in PICH.
36 */ 36 */
37static inline u64 picl_value(unsigned int nmi_hz) 37static inline u64 picl_value(unsigned int nmi_hz)
diff --git a/arch/sparc/include/asm/ptrace.h b/arch/sparc/include/asm/ptrace.h
index 30b0b797dc0c..c7ad3fe2b252 100644
--- a/arch/sparc/include/asm/ptrace.h
+++ b/arch/sparc/include/asm/ptrace.h
@@ -33,7 +33,7 @@ struct pt_regs {
33 * things like "in a system call" etc. for an arbitray 33 * things like "in a system call" etc. for an arbitray
34 * process. 34 * process.
35 * 35 *
36 * The PT_REGS_MAGIC is choosen such that it can be 36 * The PT_REGS_MAGIC is chosen such that it can be
37 * loaded completely using just a sethi instruction. 37 * loaded completely using just a sethi instruction.
38 */ 38 */
39 unsigned int magic; 39 unsigned int magic;