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author | Eric W. Biederman <ebiederm@xmission.com> | 2009-11-17 04:01:34 -0500 |
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committer | Eric W. Biederman <ebiederm@xmission.com> | 2009-11-17 04:01:34 -0500 |
commit | bb9074ff58fe745e4f244f76209241909c82ec9c (patch) | |
tree | cf6be00ab88b1e315f6b74a896a370440f677599 /arch/sparc/include/asm/system_64.h | |
parent | 4739a9748e1bd7459f22f7e94e7d85710ca83954 (diff) | |
parent | 156171c71a0dc4bce12b4408bb1591f8fe32dc1a (diff) |
Merge commit 'v2.6.32-rc7'
Resolve the conflict between v2.6.32-rc7 where dn_def_dev_handler
gets a small bug fix and the sysctl tree where I am removing all
sysctl strategy routines.
Diffstat (limited to 'arch/sparc/include/asm/system_64.h')
-rw-r--r-- | arch/sparc/include/asm/system_64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h index 25e848f0cad7..d47a98e66972 100644 --- a/arch/sparc/include/asm/system_64.h +++ b/arch/sparc/include/asm/system_64.h | |||
@@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ | |||
63 | : : : "memory"); \ | 63 | : : : "memory"); \ |
64 | } while (0) | 64 | } while (0) |
65 | 65 | ||
66 | /* The kernel always executes in TSO memory model these days, | ||
67 | * and furthermore most sparc64 chips implement more stringent | ||
68 | * memory ordering than required by the specifications. | ||
69 | */ | ||
66 | #define mb() membar_safe("#StoreLoad") | 70 | #define mb() membar_safe("#StoreLoad") |
67 | #define rmb() __asm__ __volatile__("":::"memory") | 71 | #define rmb() __asm__ __volatile__("":::"memory") |
68 | #define wmb() __asm__ __volatile__("":::"memory") | 72 | #define wmb() __asm__ __volatile__("":::"memory") |