diff options
author | Ingo Molnar <mingo@elte.hu> | 2008-07-29 05:54:24 -0400 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-07-29 05:54:24 -0400 |
commit | 3825c9e8d01e4310c40a3903a354c433c32a7b6f (patch) | |
tree | 87c94a8076bbb38bd2cf20ab9bc23d6f74f6a0a8 /arch/sparc/include/asm/sfafsr.h | |
parent | 5d7b605245b1aa1a9cd6549b1f57d69273eb0c37 (diff) | |
parent | 6e86841d05f371b5b9b86ce76c02aaee83352298 (diff) |
Merge commit 'v2.6.27-rc1' into x86/microcode
Conflicts:
arch/x86/kernel/microcode.c
Manual resolutions:
arch/x86/kernel/microcode_amd.c
arch/x86/kernel/microcode_intel.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/sparc/include/asm/sfafsr.h')
-rw-r--r-- | arch/sparc/include/asm/sfafsr.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/sfafsr.h b/arch/sparc/include/asm/sfafsr.h new file mode 100644 index 000000000000..e96137b04a4f --- /dev/null +++ b/arch/sparc/include/asm/sfafsr.h | |||
@@ -0,0 +1,82 @@ | |||
1 | #ifndef _SPARC64_SFAFSR_H | ||
2 | #define _SPARC64_SFAFSR_H | ||
3 | |||
4 | #include <linux/const.h> | ||
5 | |||
6 | /* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */ | ||
7 | |||
8 | #define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT) | ||
9 | #define SFAFSR_ME_SHIFT 32 | ||
10 | #define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT) | ||
11 | #define SFAFSR_PRIV_SHIFT 31 | ||
12 | #define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT) | ||
13 | #define SFAFSR_ISAP_SHIFT 30 | ||
14 | #define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT) | ||
15 | #define SFAFSR_ETP_SHIFT 29 | ||
16 | #define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT) | ||
17 | #define SFAFSR_IVUE_SHIFT 28 | ||
18 | #define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT) | ||
19 | #define SFAFSR_TO_SHIFT 27 | ||
20 | #define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT) | ||
21 | #define SFAFSR_BERR_SHIFT 26 | ||
22 | #define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT) | ||
23 | #define SFAFSR_LDP_SHIFT 25 | ||
24 | #define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT) | ||
25 | #define SFAFSR_CP_SHIFT 24 | ||
26 | #define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT) | ||
27 | #define SFAFSR_WP_SHIFT 23 | ||
28 | #define SFAFSR_EDP (_AC(1,UL) << SFAFSR_EDP_SHIFT) | ||
29 | #define SFAFSR_EDP_SHIFT 22 | ||
30 | #define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT) | ||
31 | #define SFAFSR_UE_SHIFT 21 | ||
32 | #define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT) | ||
33 | #define SFAFSR_CE_SHIFT 20 | ||
34 | #define SFAFSR_ETS (_AC(0xf,UL) << SFAFSR_ETS_SHIFT) | ||
35 | #define SFAFSR_ETS_SHIFT 16 | ||
36 | #define SFAFSR_PSYND (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT) | ||
37 | #define SFAFSR_PSYND_SHIFT 0 | ||
38 | |||
39 | /* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read | ||
40 | * ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write | ||
41 | */ | ||
42 | |||
43 | #define UDBE_UE (_AC(1,UL) << 9) | ||
44 | #define UDBE_CE (_AC(1,UL) << 8) | ||
45 | #define UDBE_E_SYNDR (_AC(0xff,UL) << 0) | ||
46 | |||
47 | /* The trap handlers for asynchronous errors encode the AFSR and | ||
48 | * other pieces of information into a 64-bit argument for C code | ||
49 | * encoded as follows: | ||
50 | * | ||
51 | * ----------------------------------------------- | ||
52 | * | UDB_H | UDB_L | TL>1 | TT | AFSR | | ||
53 | * ----------------------------------------------- | ||
54 | * 63 54 53 44 42 41 33 32 0 | ||
55 | * | ||
56 | * The AFAR is passed in unchanged. | ||
57 | */ | ||
58 | #define SFSTAT_UDBH_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT) | ||
59 | #define SFSTAT_UDBH_SHIFT 54 | ||
60 | #define SFSTAT_UDBL_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT) | ||
61 | #define SFSTAT_UDBL_SHIFT 44 | ||
62 | #define SFSTAT_TL_GT_ONE (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT) | ||
63 | #define SFSTAT_TL_GT_ONE_SHIFT 42 | ||
64 | #define SFSTAT_TRAP_TYPE (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT) | ||
65 | #define SFSTAT_TRAP_TYPE_SHIFT 33 | ||
66 | #define SFSTAT_AFSR_MASK (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT) | ||
67 | #define SFSTAT_AFSR_SHIFT 0 | ||
68 | |||
69 | /* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */ | ||
70 | #define ESTATE_ERR_CE 0x1 /* Correctable errors */ | ||
71 | #define ESTATE_ERR_NCE 0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */ | ||
72 | #define ESTATE_ERR_ISAP 0x4 /* System address parity error */ | ||
73 | #define ESTATE_ERR_ALL (ESTATE_ERR_CE | \ | ||
74 | ESTATE_ERR_NCE | \ | ||
75 | ESTATE_ERR_ISAP) | ||
76 | |||
77 | /* The various trap types that report using the above state. */ | ||
78 | #define TRAP_TYPE_IAE 0x09 /* Instruction Access Error */ | ||
79 | #define TRAP_TYPE_DAE 0x32 /* Data Access Error */ | ||
80 | #define TRAP_TYPE_CEE 0x63 /* Correctable ECC Error */ | ||
81 | |||
82 | #endif /* _SPARC64_SFAFSR_H */ | ||