diff options
author | Sam Ravnborg <sam@ravnborg.org> | 2014-07-20 07:39:02 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2014-07-22 00:43:19 -0400 |
commit | add79d686c81afb43dcf55924c1f11f59c5d0851 (patch) | |
tree | a5e132486fb275571d5f33b74aeca95facefd1bc /arch/sparc/include/asm/io_64.h | |
parent | be80d844c3d2c5f5b83c57f92684b37c69771ada (diff) |
sparc64: reorder functions in io_64.h
Reorder functions so __raw_{read,write}* functions comes first,
followed by {read,write}*
Update comments for the two blocks of functions.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/include/asm/io_64.h')
-rw-r--r-- | arch/sparc/include/asm/io_64.h | 234 |
1 files changed, 120 insertions, 114 deletions
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h index 6df9743270ec..6c55c532d09a 100644 --- a/arch/sparc/include/asm/io_64.h +++ b/arch/sparc/include/asm/io_64.h | |||
@@ -12,117 +12,94 @@ | |||
12 | /* BIO layer definitions. */ | 12 | /* BIO layer definitions. */ |
13 | extern unsigned long kern_base, kern_size; | 13 | extern unsigned long kern_base, kern_size; |
14 | 14 | ||
15 | #define inb inb | 15 | /* __raw_{read,write}{b,w,l,q} uses direct access. |
16 | static inline u8 inb(unsigned long addr) | 16 | * Access the memory as big endian bypassing the cache |
17 | * by using ASI_PHYS_BYPASS_EC_E | ||
18 | */ | ||
19 | #define __raw_readb __raw_readb | ||
20 | static inline u8 __raw_readb(const volatile void __iomem *addr) | ||
17 | { | 21 | { |
18 | u8 ret; | 22 | u8 ret; |
19 | 23 | ||
20 | __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */" | 24 | __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */" |
21 | : "=r" (ret) | 25 | : "=r" (ret) |
22 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | 26 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); |
23 | : "memory"); | ||
24 | 27 | ||
25 | return ret; | 28 | return ret; |
26 | } | 29 | } |
27 | 30 | ||
28 | #define inw inw | 31 | #define __raw_readw __raw_readw |
29 | static inline u16 inw(unsigned long addr) | 32 | static inline u16 __raw_readw(const volatile void __iomem *addr) |
30 | { | 33 | { |
31 | u16 ret; | 34 | u16 ret; |
32 | 35 | ||
33 | __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */" | 36 | __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */" |
34 | : "=r" (ret) | 37 | : "=r" (ret) |
35 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | 38 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); |
36 | : "memory"); | ||
37 | 39 | ||
38 | return ret; | 40 | return ret; |
39 | } | 41 | } |
40 | 42 | ||
41 | #define inl inl | 43 | #define __raw_readl __raw_readl |
42 | static inline u32 inl(unsigned long addr) | 44 | static inline u32 __raw_readl(const volatile void __iomem *addr) |
43 | { | 45 | { |
44 | u32 ret; | 46 | u32 ret; |
45 | 47 | ||
46 | __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */" | 48 | __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */" |
47 | : "=r" (ret) | 49 | : "=r" (ret) |
48 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | 50 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); |
49 | : "memory"); | ||
50 | 51 | ||
51 | return ret; | 52 | return ret; |
52 | } | 53 | } |
53 | 54 | ||
54 | #define outb outb | 55 | #define __raw_readq __raw_readq |
55 | static inline void outb(u8 b, unsigned long addr) | 56 | static inline u64 __raw_readq(const volatile void __iomem *addr) |
56 | { | ||
57 | __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */" | ||
58 | : /* no outputs */ | ||
59 | : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | ||
60 | : "memory"); | ||
61 | } | ||
62 | |||
63 | #define outw outw | ||
64 | static inline void outw(u16 w, unsigned long addr) | ||
65 | { | ||
66 | __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */" | ||
67 | : /* no outputs */ | ||
68 | : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | ||
69 | : "memory"); | ||
70 | } | ||
71 | |||
72 | #define outl outl | ||
73 | static inline void outl(u32 l, unsigned long addr) | ||
74 | { | 57 | { |
75 | __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */" | 58 | u64 ret; |
76 | : /* no outputs */ | ||
77 | : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | ||
78 | : "memory"); | ||
79 | } | ||
80 | |||
81 | |||
82 | #define inb_p(__addr) inb(__addr) | ||
83 | #define outb_p(__b, __addr) outb(__b, __addr) | ||
84 | #define inw_p(__addr) inw(__addr) | ||
85 | #define outw_p(__w, __addr) outw(__w, __addr) | ||
86 | #define inl_p(__addr) inl(__addr) | ||
87 | #define outl_p(__l, __addr) outl(__l, __addr) | ||
88 | 59 | ||
89 | void outsb(unsigned long, const void *, unsigned long); | 60 | __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */" |
90 | void outsw(unsigned long, const void *, unsigned long); | 61 | : "=r" (ret) |
91 | void outsl(unsigned long, const void *, unsigned long); | 62 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); |
92 | void insb(unsigned long, void *, unsigned long); | ||
93 | void insw(unsigned long, void *, unsigned long); | ||
94 | void insl(unsigned long, void *, unsigned long); | ||
95 | 63 | ||
96 | static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count) | 64 | return ret; |
97 | { | ||
98 | insb((unsigned long __force)port, buf, count); | ||
99 | } | ||
100 | static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count) | ||
101 | { | ||
102 | insw((unsigned long __force)port, buf, count); | ||
103 | } | 65 | } |
104 | 66 | ||
105 | static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count) | 67 | #define __raw_writeb __raw_writeb |
68 | static inline void __raw_writeb(u8 b, const volatile void __iomem *addr) | ||
106 | { | 69 | { |
107 | insl((unsigned long __force)port, buf, count); | 70 | __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */" |
71 | : /* no outputs */ | ||
72 | : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | ||
108 | } | 73 | } |
109 | 74 | ||
110 | static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count) | 75 | #define __raw_writew __raw_writew |
76 | static inline void __raw_writew(u16 w, const volatile void __iomem *addr) | ||
111 | { | 77 | { |
112 | outsb((unsigned long __force)port, buf, count); | 78 | __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */" |
79 | : /* no outputs */ | ||
80 | : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | ||
113 | } | 81 | } |
114 | 82 | ||
115 | static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count) | 83 | #define __raw_writel __raw_writel |
84 | static inline void __raw_writel(u32 l, const volatile void __iomem *addr) | ||
116 | { | 85 | { |
117 | outsw((unsigned long __force)port, buf, count); | 86 | __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */" |
87 | : /* no outputs */ | ||
88 | : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | ||
118 | } | 89 | } |
119 | 90 | ||
120 | static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count) | 91 | #define __raw_writeq __raw_writeq |
92 | static inline void __raw_writeq(u64 q, const volatile void __iomem *addr) | ||
121 | { | 93 | { |
122 | outsl((unsigned long __force)port, buf, count); | 94 | __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */" |
95 | : /* no outputs */ | ||
96 | : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | ||
123 | } | 97 | } |
124 | 98 | ||
125 | /* Memory functions, same as I/O accesses on Ultra. */ | 99 | /* Memory functions, same as I/O accesses on Ultra. |
100 | * Access memory as little endian bypassing | ||
101 | * the cache by using ASI_PHYS_BYPASS_EC_E_L | ||
102 | */ | ||
126 | #define readb readb | 103 | #define readb readb |
127 | static inline u8 readb(const volatile void __iomem *addr) | 104 | static inline u8 readb(const volatile void __iomem *addr) |
128 | { u8 ret; | 105 | { u8 ret; |
@@ -206,92 +183,121 @@ static inline void writeq(u64 q, volatile void __iomem *addr) | |||
206 | : "memory"); | 183 | : "memory"); |
207 | } | 184 | } |
208 | 185 | ||
209 | #define readb_relaxed(__addr) readb(__addr) | ||
210 | #define readw_relaxed(__addr) readw(__addr) | ||
211 | #define readl_relaxed(__addr) readl(__addr) | ||
212 | #define readq_relaxed(__addr) readq(__addr) | ||
213 | 186 | ||
214 | /* Now versions without byte-swapping. */ | 187 | #define inb inb |
215 | #define __raw_readb __raw_readb | 188 | static inline u8 inb(unsigned long addr) |
216 | static inline u8 __raw_readb(const volatile void __iomem *addr) | ||
217 | { | 189 | { |
218 | u8 ret; | 190 | u8 ret; |
219 | 191 | ||
220 | __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */" | 192 | __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */" |
221 | : "=r" (ret) | 193 | : "=r" (ret) |
222 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | 194 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
195 | : "memory"); | ||
223 | 196 | ||
224 | return ret; | 197 | return ret; |
225 | } | 198 | } |
226 | 199 | ||
227 | #define __raw_readw __raw_readw | 200 | #define inw inw |
228 | static inline u16 __raw_readw(const volatile void __iomem *addr) | 201 | static inline u16 inw(unsigned long addr) |
229 | { | 202 | { |
230 | u16 ret; | 203 | u16 ret; |
231 | 204 | ||
232 | __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */" | 205 | __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */" |
233 | : "=r" (ret) | 206 | : "=r" (ret) |
234 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | 207 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
208 | : "memory"); | ||
235 | 209 | ||
236 | return ret; | 210 | return ret; |
237 | } | 211 | } |
238 | 212 | ||
239 | #define __raw_readl __raw_readl | 213 | #define inl inl |
240 | static inline u32 __raw_readl(const volatile void __iomem *addr) | 214 | static inline u32 inl(unsigned long addr) |
241 | { | 215 | { |
242 | u32 ret; | 216 | u32 ret; |
243 | 217 | ||
244 | __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */" | 218 | __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */" |
245 | : "=r" (ret) | 219 | : "=r" (ret) |
246 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | 220 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
221 | : "memory"); | ||
247 | 222 | ||
248 | return ret; | 223 | return ret; |
249 | } | 224 | } |
250 | 225 | ||
251 | #define __raw_readq __raw_readq | 226 | #define outb outb |
252 | static inline u64 __raw_readq(const volatile void __iomem *addr) | 227 | static inline void outb(u8 b, unsigned long addr) |
253 | { | 228 | { |
254 | u64 ret; | 229 | __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */" |
255 | 230 | : /* no outputs */ | |
256 | __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */" | 231 | : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
257 | : "=r" (ret) | 232 | : "memory"); |
258 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | ||
259 | |||
260 | return ret; | ||
261 | } | 233 | } |
262 | 234 | ||
263 | #define __raw_writeb __raw_writeb | 235 | #define outw outw |
264 | static inline void __raw_writeb(u8 b, const volatile void __iomem *addr) | 236 | static inline void outw(u16 w, unsigned long addr) |
265 | { | 237 | { |
266 | __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */" | 238 | __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */" |
267 | : /* no outputs */ | 239 | : /* no outputs */ |
268 | : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | 240 | : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
241 | : "memory"); | ||
269 | } | 242 | } |
270 | 243 | ||
271 | #define __raw_writew __raw_writew | 244 | #define outl outl |
272 | static inline void __raw_writew(u16 w, const volatile void __iomem *addr) | 245 | static inline void outl(u32 l, unsigned long addr) |
273 | { | 246 | { |
274 | __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */" | 247 | __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */" |
275 | : /* no outputs */ | 248 | : /* no outputs */ |
276 | : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | 249 | : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
250 | : "memory"); | ||
277 | } | 251 | } |
278 | 252 | ||
279 | #define __raw_writel __raw_writel | 253 | |
280 | static inline void __raw_writel(u32 l, const volatile void __iomem *addr) | 254 | #define inb_p(__addr) inb(__addr) |
255 | #define outb_p(__b, __addr) outb(__b, __addr) | ||
256 | #define inw_p(__addr) inw(__addr) | ||
257 | #define outw_p(__w, __addr) outw(__w, __addr) | ||
258 | #define inl_p(__addr) inl(__addr) | ||
259 | #define outl_p(__l, __addr) outl(__l, __addr) | ||
260 | |||
261 | void outsb(unsigned long, const void *, unsigned long); | ||
262 | void outsw(unsigned long, const void *, unsigned long); | ||
263 | void outsl(unsigned long, const void *, unsigned long); | ||
264 | void insb(unsigned long, void *, unsigned long); | ||
265 | void insw(unsigned long, void *, unsigned long); | ||
266 | void insl(unsigned long, void *, unsigned long); | ||
267 | |||
268 | static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count) | ||
281 | { | 269 | { |
282 | __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */" | 270 | insb((unsigned long __force)port, buf, count); |
283 | : /* no outputs */ | 271 | } |
284 | : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | 272 | static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count) |
273 | { | ||
274 | insw((unsigned long __force)port, buf, count); | ||
285 | } | 275 | } |
286 | 276 | ||
287 | #define __raw_writeq __raw_writeq | 277 | static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count) |
288 | static inline void __raw_writeq(u64 q, const volatile void __iomem *addr) | ||
289 | { | 278 | { |
290 | __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */" | 279 | insl((unsigned long __force)port, buf, count); |
291 | : /* no outputs */ | 280 | } |
292 | : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | 281 | |
282 | static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count) | ||
283 | { | ||
284 | outsb((unsigned long __force)port, buf, count); | ||
293 | } | 285 | } |
294 | 286 | ||
287 | static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count) | ||
288 | { | ||
289 | outsw((unsigned long __force)port, buf, count); | ||
290 | } | ||
291 | |||
292 | static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count) | ||
293 | { | ||
294 | outsl((unsigned long __force)port, buf, count); | ||
295 | } | ||
296 | |||
297 | #define readb_relaxed(__addr) readb(__addr) | ||
298 | #define readw_relaxed(__addr) readw(__addr) | ||
299 | #define readl_relaxed(__addr) readl(__addr) | ||
300 | #define readq_relaxed(__addr) readq(__addr) | ||
295 | 301 | ||
296 | /* Valid I/O Space regions are anywhere, because each PCI bus supported | 302 | /* Valid I/O Space regions are anywhere, because each PCI bus supported |
297 | * can live in an arbitrary area of the physical address range. | 303 | * can live in an arbitrary area of the physical address range. |