sparc64: Add PCR ops for SPARC-T4.

This is enough to get the NMIs working, more work is needed
for perf events.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 3 insertions, 1 deletions

diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h
index 61ebe7411ceb..cc0006dc5d4a 100644
--- a/arch/sparc/include/asm/asi.h
+++ b/arch/sparc/include/asm/asi.h
@@ -141,7 +141,8 @@
 /* SpitFire and later extended ASIs.  The "(III)" marker designates
  * UltraSparc-III and later specific ASIs.  The "(CMT)" marker designates
  * Chip Multi Threading specific ASIs.  "(NG)" designates Niagara specific
- * ASIs, "(4V)" designates SUN4V specific ASIs.
+ * ASIs, "(4V)" designates SUN4V specific ASIs.  "(NG4)" designates SPARC-T4
+ * and later ASIs.
  */
 #define ASI_PHYS_USE_EC         0x14 /* PADDR, E-cachable               */
 #define ASI_PHYS_BYPASS_EC_E    0x15 /* PADDR, E-bit                    */
@@ -243,6 +244,7 @@
 #define ASI_UDBL_CONTROL_R      0x7f /* External UDB control regs rd low*/
 #define ASI_INTR_R              0x7f /* IRQ vector dispatch read        */
 #define ASI_INTR_DATAN_R        0x7f /* (III) In irq vector data reg N  */
+#define ASI_PIC                 0xb0 /* (NG4) PIC registers             */
 #define ASI_PST8_P              0xc0 /* Primary, 8 8-bit, partial       */
 #define ASI_PST8_S              0xc1 /* Secondary, 8 8-bit, partial     */
 #define ASI_PST16_P             0xc2 /* Primary, 4 16-bit, partial      */