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authorSam Ravnborg <sam@ravnborg.org>2008-07-27 17:00:59 -0400
committerSam Ravnborg <sam@ravnborg.org>2008-07-27 17:00:59 -0400
commita439fe51a1f8eb087c22dd24d69cebae4a3addac (patch)
treee32d1fa97a220ab598d8ab364205817c5bf2bd6f /arch/sparc/include/asm/apb.h
parent837b41b5de356aa67abb2cadb5eef3efc7776f91 (diff)
sparc, sparc64: use arch/sparc/include
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Diffstat (limited to 'arch/sparc/include/asm/apb.h')
-rw-r--r--arch/sparc/include/asm/apb.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/apb.h b/arch/sparc/include/asm/apb.h
new file mode 100644
index 000000000000..8f3b57db810f
--- /dev/null
+++ b/arch/sparc/include/asm/apb.h
@@ -0,0 +1,36 @@
1/*
2 * apb.h: Advanced PCI Bridge Configuration Registers and Bits
3 *
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 */
6
7#ifndef _SPARC64_APB_H
8#define _SPARC64_APB_H
9
10#define APB_TICK_REGISTER 0xb0
11#define APB_INT_ACK 0xb8
12#define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0
13#define APB_DMA_ASFR 0xc8
14#define APB_DMA_AFAR 0xd0
15#define APB_PIO_TARGET_RETRY_LIMIT 0xd8
16#define APB_PIO_TARGET_LATENCY_TIMER 0xd9
17#define APB_DMA_TARGET_RETRY_LIMIT 0xda
18#define APB_DMA_TARGET_LATENCY_TIMER 0xdb
19#define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc
20#define APB_SECONDARY_CONTROL 0xdd
21#define APB_IO_ADDRESS_MAP 0xde
22#define APB_MEM_ADDRESS_MAP 0xdf
23
24#define APB_PCI_CONTROL_LOW 0xe0
25# define APB_PCI_CTL_LOW_ARB_PARK (1 << 21)
26# define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8)
27
28#define APB_PCI_CONTROL_HIGH 0xe4
29# define APB_PCI_CTL_HIGH_SERR (1 << 2)
30# define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0)
31
32#define APB_PIO_ASFR 0xe8
33#define APB_PIO_AFAR 0xf0
34#define APB_DIAG_REGISTER 0xf8
35
36#endif /* !(_SPARC64_APB_H) */