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authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>2011-11-17 08:55:47 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-11-17 14:12:28 -0500
commit8cc88a55b03bd4940390125c2521c99368513be5 (patch)
treebad27dac59c2c8a0bf7fe3fcb5ce82cf7813c950 /arch/sh
parentd03299ee6020b0cc64fc4180162fb2e8795394e1 (diff)
sh: sh7724: use runtime PM implementation, common with arm/mach-shmobile
Switch sh7724 to a runtime PM implementation, common with ARM-based sh-mobile platforms. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/include/asm/hwblk.h5
-rw-r--r--arch/sh/kernel/cpu/Makefile5
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c157
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c121
-rw-r--r--arch/sh/kernel/cpu/shmobile/Makefile2
6 files changed, 91 insertions, 201 deletions
diff --git a/arch/sh/include/asm/hwblk.h b/arch/sh/include/asm/hwblk.h
index 855e945c6199..567c9aa1ced9 100644
--- a/arch/sh/include/asm/hwblk.h
+++ b/arch/sh/include/asm/hwblk.h
@@ -44,6 +44,7 @@ struct hwblk_info {
44 int nr_hwblks; 44 int nr_hwblks;
45}; 45};
46 46
47#if !defined(CONFIG_CPU_SUBTYPE_SH7724)
47/* Should be defined by processor-specific code */ 48/* Should be defined by processor-specific code */
48int arch_hwblk_init(void); 49int arch_hwblk_init(void);
49int arch_hwblk_sleep_mode(void); 50int arch_hwblk_sleep_mode(void);
@@ -66,5 +67,7 @@ void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int cnt);
66} 67}
67 68
68int sh_hwblk_clk_register(struct clk *clks, int nr); 69int sh_hwblk_clk_register(struct clk *clks, int nr);
69 70#else
71#define hwblk_init() 0
72#endif
70#endif /* __ASM_SH_HWBLK_H */ 73#endif /* __ASM_SH_HWBLK_H */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index ae95935d93cd..b937f1a17a4b 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -18,4 +18,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
18obj-$(CONFIG_SH_ADC) += adc.o 18obj-$(CONFIG_SH_ADC) += adc.o
19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o 19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20 20
21obj-y += irq/ init.o clock.o fpu.o hwblk.o proc.o 21obj-y += irq/ init.o clock.o fpu.o proc.o
22ifneq ($(CONFIG_CPU_SUBTYPE_SH7724),y)
23obj-y += hwblk.o
24endif
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index c57fb287011e..cb932872abad 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -29,7 +29,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o
32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o hwblk-sh7724.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35 35
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 8668f557e0ac..8df1e4ae7492 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -23,8 +23,8 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <linux/sh_clk.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
29 29
30/* SH7724 registers */ 30/* SH7724 registers */
@@ -35,6 +35,9 @@
35#define FCLKBCR 0xa415000c 35#define FCLKBCR 0xa415000c
36#define IRDACLKCR 0xa4150018 36#define IRDACLKCR 0xa4150018
37#define PLLCR 0xa4150024 37#define PLLCR 0xa4150024
38#define MSTPCR0 0xa4150030
39#define MSTPCR1 0xa4150034
40#define MSTPCR2 0xa4150038
38#define SPUCLKCR 0xa415003c 41#define SPUCLKCR 0xa415003c
39#define FLLFRQ 0xa4150050 42#define FLLFRQ 0xa4150050
40#define LSTATS 0xa4150060 43#define LSTATS 0xa4150060
@@ -196,60 +199,60 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
196}; 199};
197 200
198static struct clk mstp_clks[HWBLK_NR] = { 201static struct clk mstp_clks[HWBLK_NR] = {
199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 202 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 203 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
201 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 204 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
202 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 205 [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
203 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 206 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
204 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 207 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
205 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 208 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
206 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 209 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
207 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 210 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
208 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 211 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
209 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 212 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
210 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 213 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
211 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 214 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
212 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 215 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
213 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 216 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
214 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 217 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
215 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 218 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
216 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 219 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
217 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 220 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
218 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 221 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
219 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 222 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
220 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 223 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
221 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 224 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
222 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 225 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
223 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 226 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
224 227
225 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 228 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
226 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 229 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
227 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0), 230 [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
228 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0), 231 [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
229 232
230 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0), 233 [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),
231 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0), 234 [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),
232 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0), 235 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0),
233 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 236 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
234 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 237 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
235 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 238 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
236 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0), 239 [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0),
237 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0), 240 [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0),
238 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 241 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0),
239 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 242 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
240 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 243 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
241 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0), 244 [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0),
242 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0), 245 [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0),
243 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0), 246 [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0),
244 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0), 247 [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
245 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0), 248 [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
246 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 249 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
247 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 250 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
248 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0), 251 [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
249 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0), 252 [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
250 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0), 253 [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
251 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 254 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
252 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 255 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
253}; 256};
254 257
255static struct clk_lookup lookups[] = { 258static struct clk_lookup lookups[] = {
@@ -283,7 +286,7 @@ static struct clk_lookup lookups[] = {
283 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 286 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
284 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 287 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
285 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 288 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
286 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 289 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
287 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 290 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
288 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 291 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
289 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 292 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
@@ -294,26 +297,26 @@ static struct clk_lookup lookups[] = {
294 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]), 297 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
295 298
296 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 299 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
297 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 300 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
298 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 301 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
299 302
300 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]), 303 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
301 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]), 304 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
302 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 305 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
303 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 306 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
304 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 307 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
305 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]), 308 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
306 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]), 309 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
307 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]), 310 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
308 311
309 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 312 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
310 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 313 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
311 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 314 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
312 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 315 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
313 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]), 316 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
314 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]), 317 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
315 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 318 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]),
316 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 319 CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[HWBLK_ETHER]),
317 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 320 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
318 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 321 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
319 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 322 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
@@ -321,20 +324,20 @@ static struct clk_lookup lookups[] = {
321 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), 324 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
322 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), 325 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
323 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 326 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
324 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 327 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
325 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 328 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
326 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), 329 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
327 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]), 330 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]),
328 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), 331 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
329 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), 332 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
330 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]), 333 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
331 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 334 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
332 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 335 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
333 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), 336 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
334 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]), 337 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU0]),
335 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), 338 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
336 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 339 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
337 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 340 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
338}; 341};
339 342
340int __init arch_clk_init(void) 343int __init arch_clk_init(void)
@@ -362,7 +365,7 @@ int __init arch_clk_init(void)
362 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR); 365 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
363 366
364 if (!ret) 367 if (!ret)
365 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 368 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
366 369
367 return ret; 370 return ret;
368} 371}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
deleted file mode 100644
index 1613ad6013c3..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
3 *
4 * SH7724 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7724.h>
27
28/* SH7724 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7724 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7724_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7724_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
49 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
50 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
51 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
52 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
53 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
54 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
55 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
61 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
62 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
63 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
64 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
65 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
66 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
67 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
68 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
69
70 [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
71 [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
72 [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
74
75 [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
76 [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
77 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
78 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
79 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
80 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
81 [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
82 [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
83 [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
84 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
85 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
86 [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
87 [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
88 [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
89 [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
90 [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
91 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
92 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
93 [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
94 [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
95 [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
96 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
97 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
98};
99
100static struct hwblk_info sh7724_hwblk_info = {
101 .areas = sh7724_hwblk_area,
102 .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
103 .hwblks = sh7724_hwblk,
104 .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
105};
106
107int arch_hwblk_sleep_mode(void)
108{
109 if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
110 return SUSP_SH_STANDBY | SUSP_SH_SF;
111
112 if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
113 return SUSP_SH_SLEEP | SUSP_SH_SF;
114
115 return SUSP_SH_SLEEP;
116}
117
118int __init arch_hwblk_init(void)
119{
120 return hwblk_register(&sh7724_hwblk_info);
121}
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
index a39f88ea1a85..2f32a0352aa1 100644
--- a/arch/sh/kernel/cpu/shmobile/Makefile
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -5,4 +5,6 @@
5# Power Management & Sleep mode 5# Power Management & Sleep mode
6obj-$(CONFIG_PM) += pm.o sleep.o 6obj-$(CONFIG_PM) += pm.o sleep.o
7obj-$(CONFIG_CPU_IDLE) += cpuidle.o 7obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8ifneq ($(CONFIG_CPU_SUBTYPE_SH7724),y)
8obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o 9obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o
10endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 00:06:41 -0500