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authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>2011-11-17 08:55:56 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-11-17 14:12:29 -0500
commit7fa4632db8bfadf37b5e19f6b73398c6bccb5c90 (patch)
tree542586cd9a7b883beb11b68a5f92f0601a59ebd4 /arch/sh
parent6a06d5bf26f078212de084da93e4af863a6e5ccf (diff)
sh: sh7723: use runtime PM implementation, common with arm/mach-shmobile
Switch sh7723 to a runtime PM implementation, common with ARM-based sh-mobile platforms. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/include/asm/hwblk.h4
-rw-r--r--arch/sh/kernel/cpu/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c168
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c117
-rw-r--r--arch/sh/kernel/cpu/shmobile/Makefile2
6 files changed, 79 insertions, 216 deletions
diff --git a/arch/sh/include/asm/hwblk.h b/arch/sh/include/asm/hwblk.h
index d6b7deaaeca3..e29461bbe84d 100644
--- a/arch/sh/include/asm/hwblk.h
+++ b/arch/sh/include/asm/hwblk.h
@@ -44,7 +44,9 @@ struct hwblk_info {
44 int nr_hwblks; 44 int nr_hwblks;
45}; 45};
46 46
47#if !defined(CONFIG_CPU_SUBTYPE_SH7724) && !defined(CONFIG_CPU_SUBTYPE_SH7722) 47#if !defined(CONFIG_CPU_SUBTYPE_SH7722) && \
48 !defined(CONFIG_CPU_SUBTYPE_SH7723) && \
49 !defined(CONFIG_CPU_SUBTYPE_SH7724)
48/* Should be defined by processor-specific code */ 50/* Should be defined by processor-specific code */
49int arch_hwblk_init(void); 51int arch_hwblk_init(void);
50int arch_hwblk_sleep_mode(void); 52int arch_hwblk_sleep_mode(void);
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index b1f515cb4c79..5366fdf8c566 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -19,6 +19,6 @@ obj-$(CONFIG_SH_ADC) += adc.o
19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o 19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20 20
21obj-y += irq/ init.o clock.o fpu.o proc.o 21obj-y += irq/ init.o clock.o fpu.o proc.o
22ifneq ($(CONFIG_CPU_SUBTYPE_SH7724)$(CONFIG_CPU_SUBTYPE_SH7722),y) 22ifneq ($(CONFIG_CPU_SUBTYPE_SH7722)$(CONFIG_CPU_SUBTYPE_SH7723)$(CONFIG_CPU_SUBTYPE_SH7724),y)
23obj-y += hwblk.o 23obj-y += hwblk.o
24endif 24endif
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 9f28773d678d..0b22d108f4c5 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -28,7 +28,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 3cc3827380e3..041c415e9c4e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -23,8 +23,8 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <linux/sh_clk.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7723.h> 28#include <cpu/sh7723.h>
29 29
30/* SH7723 registers */ 30/* SH7723 registers */
@@ -34,6 +34,9 @@
34#define SCLKBCR 0xa415000c 34#define SCLKBCR 0xa415000c
35#define IRDACLKCR 0xa4150018 35#define IRDACLKCR 0xa4150018
36#define PLLCR 0xa4150024 36#define PLLCR 0xa4150024
37#define MSTPCR0 0xa4150030
38#define MSTPCR1 0xa4150034
39#define MSTPCR2 0xa4150038
37#define DLLFRQ 0xa4150050 40#define DLLFRQ 0xa4150050
38 41
39/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 42/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -149,55 +152,55 @@ struct clk div6_clks[DIV6_NR] = {
149 152
150static struct clk mstp_clks[] = { 153static struct clk mstp_clks[] = {
151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 154 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 155 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 156 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 157 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 158 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 159 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 160 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 161 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 162 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 163 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 164 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 165 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 166 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 167 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 168 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 169 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 170 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 171 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 172 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 173 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 174 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 175 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 176 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 177 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 178 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 179 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0), 180 [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
178 181
179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 182 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 183 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
181 184
182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0), 185 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0), 186 [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 187 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 188 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 189 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 190 [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 191 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 192 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 193 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0), 194 [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0),
192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 195 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0),
193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 196 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0), 197 [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 198 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 199 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 200 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0), 201 [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 202 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 203 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
201}; 204};
202 205
203static struct clk_lookup lookups[] = { 206static struct clk_lookup lookups[] = {
@@ -229,7 +232,7 @@ static struct clk_lookup lookups[] = {
229 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 232 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
230 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 233 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
231 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 234 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
232 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 235 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
233 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 236 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
234 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 237 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
235 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 238 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
@@ -250,8 +253,8 @@ static struct clk_lookup lookups[] = {
250 .clk = &mstp_clks[HWBLK_TMU0], 253 .clk = &mstp_clks[HWBLK_TMU0],
251 }, 254 },
252 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 255 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
253 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 256 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
254 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 257 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
255 { 258 {
256 /* TMU3 */ 259 /* TMU3 */
257 .dev_id = "sh_tmu.3", 260 .dev_id = "sh_tmu.3",
@@ -269,40 +272,15 @@ static struct clk_lookup lookups[] = {
269 .clk = &mstp_clks[HWBLK_TMU1], 272 .clk = &mstp_clks[HWBLK_TMU1],
270 }, 273 },
271 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 274 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
272 { 275 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
273 /* SCIF0 */ 276 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
274 .dev_id = "sh-sci.0", 277 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
275 .con_id = "sci_fck", 278 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
276 .clk = &mstp_clks[HWBLK_SCIF0], 279 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
277 }, { 280 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
278 /* SCIF1 */ 281 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
279 .dev_id = "sh-sci.1", 282 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
280 .con_id = "sci_fck", 283 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[HWBLK_MERAM]),
281 .clk = &mstp_clks[HWBLK_SCIF1],
282 }, {
283 /* SCIF2 */
284 .dev_id = "sh-sci.2",
285 .con_id = "sci_fck",
286 .clk = &mstp_clks[HWBLK_SCIF2],
287 }, {
288 /* SCIF3 */
289 .dev_id = "sh-sci.3",
290 .con_id = "sci_fck",
291 .clk = &mstp_clks[HWBLK_SCIF3],
292 }, {
293 /* SCIF4 */
294 .dev_id = "sh-sci.4",
295 .con_id = "sci_fck",
296 .clk = &mstp_clks[HWBLK_SCIF4],
297 }, {
298 /* SCIF5 */
299 .dev_id = "sh-sci.5",
300 .con_id = "sci_fck",
301 .clk = &mstp_clks[HWBLK_SCIF5],
302 },
303 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
304 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
305 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
306 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 284 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
307 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 285 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
308 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 286 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
@@ -311,19 +289,19 @@ static struct clk_lookup lookups[] = {
311 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 289 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
312 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 290 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
313 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]), 291 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
314 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 292 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
315 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 293 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
316 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 294 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
317 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]), 295 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
318 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 296 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
319 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), 297 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
320 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]), 298 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
321 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 299 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
322 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 300 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
323 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), 301 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
324 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]), 302 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
325 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 303 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
326 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 304 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
327}; 305};
328 306
329int __init arch_clk_init(void) 307int __init arch_clk_init(void)
@@ -356,7 +334,7 @@ int __init arch_clk_init(void)
356 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 334 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
357 335
358 if (!ret) 336 if (!ret)
359 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 337 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
360 338
361 return ret; 339 return ret;
362} 340}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
deleted file mode 100644
index a7f4684d2032..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
3 *
4 * SH7723 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7723.h>
27
28/* SH7723 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7723 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7723_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7723_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
49 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
50 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
51 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
52 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
53 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
54 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
55 [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA),
61 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
62 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
63 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
64 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
65 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
66 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
67 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
68 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
69 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
70 [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA),
71
72 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
74
75 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
76 [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
77 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
78 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
79 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
80 [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
81 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
82 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
83 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
84 [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA),
85 [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
86 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
87 [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
88 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
89 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
90 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
91 [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
92 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
93 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
94};
95
96static struct hwblk_info sh7723_hwblk_info = {
97 .areas = sh7723_hwblk_area,
98 .nr_areas = ARRAY_SIZE(sh7723_hwblk_area),
99 .hwblks = sh7723_hwblk,
100 .nr_hwblks = ARRAY_SIZE(sh7723_hwblk),
101};
102
103int arch_hwblk_sleep_mode(void)
104{
105 if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
106 return SUSP_SH_STANDBY | SUSP_SH_SF;
107
108 if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
109 return SUSP_SH_SLEEP | SUSP_SH_SF;
110
111 return SUSP_SH_SLEEP;
112}
113
114int __init arch_hwblk_init(void)
115{
116 return hwblk_register(&sh7723_hwblk_info);
117}
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
index e83c9d55ccd9..7eb4502dfb61 100644
--- a/arch/sh/kernel/cpu/shmobile/Makefile
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -5,6 +5,6 @@
5# Power Management & Sleep mode 5# Power Management & Sleep mode
6obj-$(CONFIG_PM) += pm.o sleep.o 6obj-$(CONFIG_PM) += pm.o sleep.o
7obj-$(CONFIG_CPU_IDLE) += cpuidle.o 7obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8ifneq ($(CONFIG_CPU_SUBTYPE_SH7724)$(CONFIG_CPU_SUBTYPE_SH7722),y) 8ifneq ($(CONFIG_CPU_SUBTYPE_SH7722)$(CONFIG_CPU_SUBTYPE_SH7723)$(CONFIG_CPU_SUBTYPE_SH7724),y)
9obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o 9obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o
10endif 10endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 13:19:40 -0500