aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh
diff options
context:
space:
mode:
authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2010-11-26 04:40:22 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-11-28 22:59:22 -0500
commit4bd5d259e451d35380de2fcd1a3510ae22d000a3 (patch)
treef236004a7223a089b360bd33ce9f31340a3268a0 /arch/sh
parente5843341e3ad8ff00332376cd0745026e4b5d45f (diff)
sh: Add div6_reparent_clks to clock framework for FSI
Current clk_ops doesn't support .init which is used to select external clock on ecovec without CONFIG_SH_CLK_CPG_LEGACY. To solve this problem, this patch add div6_reparent_clks to clock-sh7724. This patch solve compile error too. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c34
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7724.h3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c44
3 files changed, 46 insertions, 35 deletions
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 2eaeb9e59585..f48c492a68d3 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -720,32 +720,6 @@ static struct platform_device camera_devices[] = {
720}; 720};
721 721
722/* FSI */ 722/* FSI */
723/*
724 * FSI-B use external clock which came from da7210.
725 * So, we should change parent of fsi
726 */
727#define FCLKBCR 0xa415000c
728static void fsimck_init(struct clk *clk)
729{
730 u32 status = __raw_readl(clk->enable_reg);
731
732 /* use external clock */
733 status &= ~0x000000ff;
734 status |= 0x00000080;
735
736 __raw_writel(status, clk->enable_reg);
737}
738
739static struct clk_ops fsimck_clk_ops = {
740 .init = fsimck_init,
741};
742
743static struct clk fsimckb_clk = {
744 .ops = &fsimck_clk_ops,
745 .enable_reg = (void __iomem *)FCLKBCR,
746 .rate = 0, /* unknown */
747};
748
749static struct sh_fsi_platform_info fsi_info = { 723static struct sh_fsi_platform_info fsi_info = {
750 .portb_flags = SH_FSI_BRS_INV | 724 .portb_flags = SH_FSI_BRS_INV |
751 SH_FSI_OUT_SLAVE_MODE | 725 SH_FSI_OUT_SLAVE_MODE |
@@ -1264,10 +1238,10 @@ static int __init arch_setup(void)
1264 /* change parent of FSI B */ 1238 /* change parent of FSI B */
1265 clk = clk_get(NULL, "fsib_clk"); 1239 clk = clk_get(NULL, "fsib_clk");
1266 if (!IS_ERR(clk)) { 1240 if (!IS_ERR(clk)) {
1267 clk_register(&fsimckb_clk); 1241 /* 48kHz dummy clock was used to make sure 1/1 divide */
1268 clk_set_parent(clk, &fsimckb_clk); 1242 clk_set_rate(&sh7724_fsimckb_clk, 48000);
1269 clk_set_rate(clk, 11000); 1243 clk_set_parent(clk, &sh7724_fsimckb_clk);
1270 clk_set_rate(&fsimckb_clk, 11000); 1244 clk_set_rate(clk, 48000);
1271 clk_put(clk); 1245 clk_put(clk);
1272 } 1246 }
1273 1247
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
index 4c27b68789b3..7eb435999426 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7724.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -303,4 +303,7 @@ enum {
303 SHDMA_SLAVE_SDHI1_RX, 303 SHDMA_SLAVE_SDHI1_RX,
304}; 304};
305 305
306extern struct clk sh7724_fsimcka_clk;
307extern struct clk sh7724_fsimckb_clk;
308
306#endif /* __ASM_SH7724_H__ */ 309#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 0fe2e9329cb2..271c0b325a9a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -111,12 +111,21 @@ static struct clk div3_clk = {
111 .parent = &pll_clk, 111 .parent = &pll_clk,
112}; 112};
113 113
114/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
115struct clk sh7724_fsimcka_clk = {
116};
117
118struct clk sh7724_fsimckb_clk = {
119};
120
114static struct clk *main_clks[] = { 121static struct clk *main_clks[] = {
115 &r_clk, 122 &r_clk,
116 &extal_clk, 123 &extal_clk,
117 &fll_clk, 124 &fll_clk,
118 &pll_clk, 125 &pll_clk,
119 &div3_clk, 126 &div3_clk,
127 &sh7724_fsimcka_clk,
128 &sh7724_fsimckb_clk,
120}; 129};
121 130
122static void div4_kick(struct clk *clk) 131static void div4_kick(struct clk *clk)
@@ -154,16 +163,38 @@ struct clk div4_clks[DIV4_NR] = {
154 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 163 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
155}; 164};
156 165
157enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; 166enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
158 167
159static struct clk div6_clks[DIV6_NR] = { 168static struct clk div6_clks[DIV6_NR] = {
160 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 169 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
161 [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
162 [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
163 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 170 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
164 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 171 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
165}; 172};
166 173
174enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
175
176/* Indices are important - they are the actual src selecting values */
177static struct clk *fclkacr_parent[] = {
178 [0] = &div3_clk,
179 [1] = NULL,
180 [2] = &sh7724_fsimcka_clk,
181 [3] = NULL,
182};
183
184static struct clk *fclkbcr_parent[] = {
185 [0] = &div3_clk,
186 [1] = NULL,
187 [2] = &sh7724_fsimckb_clk,
188 [3] = NULL,
189};
190
191static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
192 [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
193 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
194 [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
195 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
196};
197
167static struct clk mstp_clks[HWBLK_NR] = { 198static struct clk mstp_clks[HWBLK_NR] = {
168 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
@@ -240,8 +271,8 @@ static struct clk_lookup lookups[] = {
240 271
241 /* DIV6 clocks */ 272 /* DIV6 clocks */
242 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 273 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
243 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), 274 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
244 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]), 275 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
245 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 276 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
246 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 277 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
247 278
@@ -376,6 +407,9 @@ int __init arch_clk_init(void)
376 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 407 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
377 408
378 if (!ret) 409 if (!ret)
410 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
411
412 if (!ret)
379 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 413 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
380 414
381 return ret; 415 return ret;