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authorPaul Mundt <lethal@linux-sh.org>2009-11-09 00:11:07 -0500
committerPaul Mundt <lethal@linux-sh.org>2009-11-09 00:11:07 -0500
commit0fe69d773f35fd95938ea02a91ec2d026045398b (patch)
tree4ed85099151c687daa2b8b0bf0ec7233a4528681 /arch/sh
parent76d2318020bf0c0c497af986a25977196715a1b9 (diff)
sh: perf events: Document SH-4A raw event codes.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh4a/perf_event.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
index d0938345799f..eddc21973fa1 100644
--- a/arch/sh/kernel/cpu/sh4a/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -38,6 +38,44 @@
38static struct sh_pmu sh4a_pmu; 38static struct sh_pmu sh4a_pmu;
39 39
40/* 40/*
41 * Supported raw event codes:
42 *
43 * Event Code Description
44 * ---------- -----------
45 *
46 * 0x0000 number of elapsed cycles
47 * 0x0200 number of elapsed cycles in privileged mode
48 * 0x0280 number of elapsed cycles while SR.BL is asserted
49 * 0x0202 instruction execution
50 * 0x0203 instruction execution in parallel
51 * 0x0204 number of unconditional branches
52 * 0x0208 number of exceptions
53 * 0x0209 number of interrupts
54 * 0x0220 UTLB miss caused by instruction fetch
55 * 0x0222 UTLB miss caused by operand access
56 * 0x02a0 number of ITLB misses
57 * 0x0028 number of accesses to instruction memories
58 * 0x0029 number of accesses to instruction cache
59 * 0x002a instruction cache miss
60 * 0x022e number of access to instruction X/Y memory
61 * 0x0030 number of reads to operand memories
62 * 0x0038 number of writes to operand memories
63 * 0x0031 number of operand cache read accesses
64 * 0x0039 number of operand cache write accesses
65 * 0x0032 operand cache read miss
66 * 0x003a operand cache write miss
67 * 0x0236 number of reads to operand X/Y memory
68 * 0x023e number of writes to operand X/Y memory
69 * 0x0237 number of reads to operand U memory
70 * 0x023f number of writes to operand U memory
71 * 0x0337 number of U memory read buffer misses
72 * 0x02b4 number of wait cycles due to operand read access
73 * 0x02bc number of wait cycles due to operand write access
74 * 0x0033 number of wait cycles due to operand cache read miss
75 * 0x003b number of wait cycles due to operand cache write miss
76 */
77
78/*
41 * Special reserved bits used by hardware emulators, read values will 79 * Special reserved bits used by hardware emulators, read values will
42 * vary, but writes must always be 0. 80 * vary, but writes must always be 0.
43 */ 81 */