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authorMagnus Damm <damm@igel.co.jp>2009-05-12 06:25:54 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-05-12 06:53:14 -0400
commitf19900b2e608b604777a74d6d711bbf744657756 (patch)
treebf588e8de67316adc5d26c62a1d3c86b9f556e7d /arch/sh
parent2b23a8826a60268ec52302729911dd7ac6b10776 (diff)
sh: remove old TMU driver
This patch removes the old TMU driver (CONFIG_SH_TMU/timer-tmu.c) As replacement, select the sh_tmu driver with CONFIG_SH_TIMER_TMU and configure timer channel using platform data. If multiple TMU channels are enabled using platform data, use the earlytimer parameter on the kernel command line to select channel. For instance, use "earlytimer=sh_tmu.0" to select the first channel. To verify which timer is being used, look at printouts or the timer irq count in /proc/interrupts. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/Kconfig9
-rw-r--r--arch/sh/include/asm/timer.h1
-rw-r--r--arch/sh/include/cpu-sh3/cpu/timer.h67
-rw-r--r--arch/sh/include/cpu-sh4/cpu/timer.h60
-rw-r--r--arch/sh/kernel/timers/Makefile2
-rw-r--r--arch/sh/kernel/timers/timer-tmu.c297
-rw-r--r--arch/sh/kernel/timers/timer.c3
7 files changed, 1 insertions, 438 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 5391746be1e9..e7b6406c96b6 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -473,16 +473,9 @@ source "arch/sh/boards/Kconfig"
473 473
474menu "Timer and clock configuration" 474menu "Timer and clock configuration"
475 475
476config SH_TMU
477 bool "TMU timer support"
478 depends on CPU_SH3 || CPU_SH4
479 default y
480 help
481 This enables the use of the TMU as the system timer.
482
483config SH_TIMER_TMU 476config SH_TIMER_TMU
484 bool "TMU timer driver" 477 bool "TMU timer driver"
485 depends on !SH_TMU && SYS_SUPPORTS_TMU 478 depends on SYS_SUPPORTS_TMU
486 default y 479 default y
487 help 480 help
488 This enables the build of the TMU timer driver. 481 This enables the build of the TMU timer driver.
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
index 6c0851188c00..f27a88bfdcc7 100644
--- a/arch/sh/include/asm/timer.h
+++ b/arch/sh/include/asm/timer.h
@@ -18,7 +18,6 @@ struct sys_timer {
18 struct sys_timer_ops *ops; 18 struct sys_timer_ops *ops;
19}; 19};
20 20
21extern struct sys_timer tmu_timer;
22extern struct sys_timer *sys_timer; 21extern struct sys_timer *sys_timer;
23 22
24/* arch/sh/kernel/timers/timer.c */ 23/* arch/sh/kernel/timers/timer.c */
diff --git a/arch/sh/include/cpu-sh3/cpu/timer.h b/arch/sh/include/cpu-sh3/cpu/timer.h
deleted file mode 100644
index 793acf12aa08..000000000000
--- a/arch/sh/include/cpu-sh3/cpu/timer.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_TIMER_H
11#define __ASM_CPU_SH3_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH3 processors
16 * SH7706
17 * SH7709S
18 * SH7727
19 * SH7729R
20 * SH7710
21 * SH7720
22 * SH7710
23 * ---------------------------------------------------------------------------
24 */
25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
27#define TMU_TOCR 0xfffffe90 /* Byte access */
28#endif
29
30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7721)
33#define TMU_012_TSTR 0xa412fe92 /* Byte access */
34
35#define TMU0_TCOR 0xa412fe94 /* Long access */
36#define TMU0_TCNT 0xa412fe98 /* Long access */
37#define TMU0_TCR 0xa412fe9c /* Word access */
38
39#define TMU1_TCOR 0xa412fea0 /* Long access */
40#define TMU1_TCNT 0xa412fea4 /* Long access */
41#define TMU1_TCR 0xa412fea8 /* Word access */
42
43#define TMU2_TCOR 0xa412feac /* Long access */
44#define TMU2_TCNT 0xa412feb0 /* Long access */
45#define TMU2_TCR 0xa412feb4 /* Word access */
46
47#else
48#define TMU_012_TSTR 0xfffffe92 /* Byte access */
49
50#define TMU0_TCOR 0xfffffe94 /* Long access */
51#define TMU0_TCNT 0xfffffe98 /* Long access */
52#define TMU0_TCR 0xfffffe9c /* Word access */
53
54#define TMU1_TCOR 0xfffffea0 /* Long access */
55#define TMU1_TCNT 0xfffffea4 /* Long access */
56#define TMU1_TCR 0xfffffea8 /* Word access */
57
58#define TMU2_TCOR 0xfffffeac /* Long access */
59#define TMU2_TCNT 0xfffffeb0 /* Long access */
60#define TMU2_TCR 0xfffffeb4 /* Word access */
61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
62#define TMU2_TCPR2 0xfffffeb8 /* Long access */
63#endif
64#endif
65
66#endif /* __ASM_CPU_SH3_TIMER_H */
67
diff --git a/arch/sh/include/cpu-sh4/cpu/timer.h b/arch/sh/include/cpu-sh4/cpu/timer.h
deleted file mode 100644
index d1e796b96888..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/timer.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_TIMER_H
11#define __ASM_CPU_SH4_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH4 processors
16 * SH7750S/SH7750R
17 * SH7751/SH7751R
18 * SH7760
19 * SH-X3
20 * ---------------------------------------------------------------------------
21 */
22#ifdef CONFIG_CPU_SUBTYPE_SHX3
23#define TMU_012_BASE 0xffc10000
24#define TMU_345_BASE 0xffc20000
25#else
26#define TMU_012_BASE 0xffd80000
27#define TMU_345_BASE 0xfe100000
28#endif
29
30#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
31
32#define TMU_012_TSTR (TMU_012_BASE + 0x04)
33#define TMU_345_TSTR (TMU_345_BASE + 0x04)
34
35#define TMU0_TCOR (TMU_012_BASE + 0x08)
36#define TMU0_TCNT (TMU_012_BASE + 0x0c)
37#define TMU0_TCR (TMU_012_BASE + 0x10)
38
39#define TMU1_TCOR (TMU_012_BASE + 0x14)
40#define TMU1_TCNT (TMU_012_BASE + 0x18)
41#define TMU1_TCR (TMU_012_BASE + 0x1c)
42
43#define TMU2_TCOR (TMU_012_BASE + 0x20)
44#define TMU2_TCNT (TMU_012_BASE + 0x24)
45#define TMU2_TCR (TMU_012_BASE + 0x28)
46#define TMU2_TCPR (TMU_012_BASE + 0x2c)
47
48#define TMU3_TCOR (TMU_345_BASE + 0x08)
49#define TMU3_TCNT (TMU_345_BASE + 0x0c)
50#define TMU3_TCR (TMU_345_BASE + 0x10)
51
52#define TMU4_TCOR (TMU_345_BASE + 0x14)
53#define TMU4_TCNT (TMU_345_BASE + 0x18)
54#define TMU4_TCR (TMU_345_BASE + 0x1c)
55
56#define TMU5_TCOR (TMU_345_BASE + 0x20)
57#define TMU5_TCNT (TMU_345_BASE + 0x24)
58#define TMU5_TCR (TMU_345_BASE + 0x28)
59
60#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/arch/sh/kernel/timers/Makefile b/arch/sh/kernel/timers/Makefile
index 8bceba59e76f..fefd7edd413d 100644
--- a/arch/sh/kernel/timers/Makefile
+++ b/arch/sh/kernel/timers/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y := timer.o 5obj-y := timer.o
6
7obj-$(CONFIG_SH_TMU) += timer-tmu.o
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
deleted file mode 100644
index fe8d8930ccb6..000000000000
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ /dev/null
@@ -1,297 +0,0 @@
1/*
2 * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
3 *
4 * Copyright (C) 2005 - 2007 Paul Mundt
5 *
6 * TMU handling code hacked out of arch/sh/kernel/time.c
7 *
8 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
9 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
10 * Copyright (C) 2002, 2003, 2004 Paul Mundt
11 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/interrupt.h>
20#include <linux/seqlock.h>
21#include <linux/clockchips.h>
22#include <asm/timer.h>
23#include <asm/rtc.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26#include <asm/clock.h>
27
28#define TMU_TOCR_INIT 0x00
29#define TMU_TCR_INIT 0x0020
30
31#define TMU0 (0)
32#define TMU1 (1)
33
34static inline void _tmu_start(int tmu_num)
35{
36 ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
37}
38
39static inline void _tmu_set_irq(int tmu_num, int enabled)
40{
41 register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
42 ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
43}
44
45static inline void _tmu_stop(int tmu_num)
46{
47 ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
48}
49
50static inline void _tmu_clear_status(int tmu_num)
51{
52 register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
53 /* Clear UNF bit */
54 ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
55}
56
57static inline unsigned long _tmu_read(int tmu_num)
58{
59 return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
60}
61
62static int tmu_timer_start(void)
63{
64 _tmu_start(TMU0);
65 _tmu_start(TMU1);
66 _tmu_set_irq(TMU0,1);
67 return 0;
68}
69
70static int tmu_timer_stop(void)
71{
72 _tmu_stop(TMU0);
73 _tmu_stop(TMU1);
74 _tmu_clear_status(TMU0);
75 return 0;
76}
77
78/*
79 * also when the module_clk is scaled the TMU1
80 * will show the same frequency
81 */
82static int tmus_are_scaled;
83
84static cycle_t tmu_timer_read(struct clocksource *cs)
85{
86 return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
87}
88
89
90static unsigned long tmu_latest_interval[3];
91static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
92{
93 unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
94 unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
95
96 _tmu_stop(tmu_num);
97
98 ctrl_outl(interval, tmu_tcnt);
99 tmu_latest_interval[tmu_num] = interval;
100
101 /*
102 * TCNT reloads from TCOR on underflow, clear it if we don't
103 * intend to auto-reload
104 */
105 ctrl_outl( reload ? interval : 0 , tmu_tcor);
106
107 _tmu_start(tmu_num);
108}
109
110static int tmu_set_next_event(unsigned long cycles,
111 struct clock_event_device *evt)
112{
113 tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
114 _tmu_set_irq(TMU0,1);
115 return 0;
116}
117
118static void tmu_set_mode(enum clock_event_mode mode,
119 struct clock_event_device *evt)
120{
121 switch (mode) {
122 case CLOCK_EVT_MODE_PERIODIC:
123 ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
124 break;
125 case CLOCK_EVT_MODE_ONESHOT:
126 ctrl_outl(0, TMU0_TCOR);
127 break;
128 case CLOCK_EVT_MODE_UNUSED:
129 case CLOCK_EVT_MODE_SHUTDOWN:
130 case CLOCK_EVT_MODE_RESUME:
131 break;
132 }
133}
134
135static struct clock_event_device tmu0_clockevent = {
136 .name = "tmu0",
137 .shift = 32,
138 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
139 .set_mode = tmu_set_mode,
140 .set_next_event = tmu_set_next_event,
141};
142
143static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
144{
145 struct clock_event_device *evt = &tmu0_clockevent;
146 _tmu_clear_status(TMU0);
147 _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
148
149 switch (tmu0_clockevent.mode) {
150 case CLOCK_EVT_MODE_ONESHOT:
151 case CLOCK_EVT_MODE_PERIODIC:
152 evt->event_handler(evt);
153 break;
154 default:
155 break;
156 }
157
158 return IRQ_HANDLED;
159}
160
161static struct irqaction tmu0_irq = {
162 .name = "periodic/oneshot timer",
163 .handler = tmu_timer_interrupt,
164 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
165};
166
167static void __init tmu_clk_init(struct clk *clk)
168{
169 u8 divisor = TMU_TCR_INIT & 0x7;
170 int tmu_num = clk->name[3]-'0';
171 ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
172 clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
173}
174
175static void tmu_clk_recalc(struct clk *clk)
176{
177 int tmu_num = clk->name[3]-'0';
178 unsigned long prev_rate = clk_get_rate(clk);
179 unsigned long flags;
180 u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
181 clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
182
183 if(prev_rate==clk_get_rate(clk))
184 return;
185
186 if(tmu_num)
187 return; /* No more work on TMU1 */
188
189 local_irq_save(flags);
190 tmus_are_scaled = (prev_rate > clk->rate);
191
192 _tmu_stop(TMU0);
193
194 tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
195 tmu0_clockevent.shift);
196 tmu0_clockevent.max_delta_ns =
197 clockevent_delta2ns(-1, &tmu0_clockevent);
198 tmu0_clockevent.min_delta_ns =
199 clockevent_delta2ns(1, &tmu0_clockevent);
200
201 if (tmus_are_scaled)
202 tmu_latest_interval[TMU0] >>= 1;
203 else
204 tmu_latest_interval[TMU0] <<= 1;
205
206 tmu_timer_set_interval(TMU0,
207 tmu_latest_interval[TMU0],
208 tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
209
210 _tmu_start(TMU0);
211
212 local_irq_restore(flags);
213}
214
215static struct clk_ops tmu_clk_ops = {
216 .init = tmu_clk_init,
217 .recalc = tmu_clk_recalc,
218};
219
220static struct clk tmu0_clk = {
221 .name = "tmu0_clk",
222 .ops = &tmu_clk_ops,
223};
224
225static struct clk tmu1_clk = {
226 .name = "tmu1_clk",
227 .ops = &tmu_clk_ops,
228};
229
230static int tmu_timer_init(void)
231{
232 unsigned long interval;
233 unsigned long frequency;
234
235 setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
236
237 tmu0_clk.parent = clk_get(NULL, "module_clk");
238 tmu1_clk.parent = clk_get(NULL, "module_clk");
239
240 tmu_timer_stop();
241
242#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
243 !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
244 !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
245 !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
246 !defined(CONFIG_CPU_SUBTYPE_SH7786) && \
247 !defined(CONFIG_CPU_SUBTYPE_SHX3)
248 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
249#endif
250
251 clk_register(&tmu0_clk);
252 clk_register(&tmu1_clk);
253 clk_enable(&tmu0_clk);
254 clk_enable(&tmu1_clk);
255
256 frequency = clk_get_rate(&tmu0_clk);
257 interval = (frequency + HZ / 2) / HZ;
258
259 tmu_timer_set_interval(TMU0,interval, 1);
260 tmu_timer_set_interval(TMU1,~0,1);
261
262 _tmu_start(TMU1);
263
264 clocksource_sh.rating = 200;
265 clocksource_sh.mask = CLOCKSOURCE_MASK(32);
266 clocksource_sh.read = tmu_timer_read;
267 clocksource_sh.shift = 10;
268 clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
269 clocksource_sh.shift);
270 clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
271 clocksource_register(&clocksource_sh);
272
273 tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
274 tmu0_clockevent.shift);
275 tmu0_clockevent.max_delta_ns =
276 clockevent_delta2ns(-1, &tmu0_clockevent);
277 tmu0_clockevent.min_delta_ns =
278 clockevent_delta2ns(1, &tmu0_clockevent);
279
280 tmu0_clockevent.cpumask = cpumask_of(0);
281 tmu0_clockevent.rating = 100;
282
283 clockevents_register_device(&tmu0_clockevent);
284
285 return 0;
286}
287
288static struct sys_timer_ops tmu_timer_ops = {
289 .init = tmu_timer_init,
290 .start = tmu_timer_start,
291 .stop = tmu_timer_stop,
292};
293
294struct sys_timer tmu_timer = {
295 .name = "tmu",
296 .ops = &tmu_timer_ops,
297};
diff --git a/arch/sh/kernel/timers/timer.c b/arch/sh/kernel/timers/timer.c
index 920891acb779..f8812bd3b797 100644
--- a/arch/sh/kernel/timers/timer.c
+++ b/arch/sh/kernel/timers/timer.c
@@ -14,9 +14,6 @@
14#include <asm/timer.h> 14#include <asm/timer.h>
15 15
16static struct sys_timer *sys_timers[] = { 16static struct sys_timer *sys_timers[] = {
17#ifdef CONFIG_SH_TMU
18 &tmu_timer,
19#endif
20 NULL, 17 NULL,
21}; 18};
22 19
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