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authorMagnus Damm <damm@igel.co.jp>2008-07-17 05:56:15 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-07-28 05:10:36 -0400
commitaea167cbb5c9056295109e5e171d27e30e2be5bc (patch)
treeee87d1120afa05de35b9fd9fe5dc1c0b195d2a65 /arch/sh
parent3fec18bd603c3a55aeb325121a3e752f647641be (diff)
sh: Add SuperH Mobile MSTPCR bits to clock framework
Handle module stop clock bits in MSTPCRn through the clock framework. The clocks are named after the bits in the data sheet. The association between bit number and hardware block is processor specific. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c116
1 files changed, 116 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index d7b14660f737..2f50f8a1f878 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -14,6 +14,7 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/errno.h> 16#include <linux/errno.h>
17#include <linux/stringify.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/freq.h> 19#include <asm/freq.h>
19 20
@@ -558,6 +559,115 @@ static struct clk sh7722_video_clock = {
558 .ops = &sh7722_video_clk_ops, 559 .ops = &sh7722_video_clk_ops,
559}; 560};
560 561
562static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg,
563 int enable)
564{
565 unsigned long bit = clk->arch_flags;
566 unsigned long r;
567
568 r = ctrl_inl(reg);
569
570 if (enable)
571 r &= ~(1 << bit);
572 else
573 r |= (1 << bit);
574
575 ctrl_outl(r, reg);
576 return 0;
577}
578
579static void sh7722_mstpcr0_enable(struct clk *clk)
580{
581 sh7722_mstpcr_start_stop(clk, MSTPCR0, 1);
582}
583
584static void sh7722_mstpcr0_disable(struct clk *clk)
585{
586 sh7722_mstpcr_start_stop(clk, MSTPCR0, 0);
587}
588
589static void sh7722_mstpcr1_enable(struct clk *clk)
590{
591 sh7722_mstpcr_start_stop(clk, MSTPCR1, 1);
592}
593
594static void sh7722_mstpcr1_disable(struct clk *clk)
595{
596 sh7722_mstpcr_start_stop(clk, MSTPCR1, 0);
597}
598
599static void sh7722_mstpcr2_enable(struct clk *clk)
600{
601 sh7722_mstpcr_start_stop(clk, MSTPCR2, 1);
602}
603
604static void sh7722_mstpcr2_disable(struct clk *clk)
605{
606 sh7722_mstpcr_start_stop(clk, MSTPCR2, 0);
607}
608
609static struct clk_ops sh7722_mstpcr0_clk_ops = {
610 .enable = sh7722_mstpcr0_enable,
611 .disable = sh7722_mstpcr0_disable,
612};
613
614static struct clk_ops sh7722_mstpcr1_clk_ops = {
615 .enable = sh7722_mstpcr1_enable,
616 .disable = sh7722_mstpcr1_disable,
617};
618
619static struct clk_ops sh7722_mstpcr2_clk_ops = {
620 .enable = sh7722_mstpcr2_enable,
621 .disable = sh7722_mstpcr2_disable,
622};
623
624#define DECLARE_MSTPCRN(regnr, bitnr, bitstr) \
625{ \
626 .name = "mstp" __stringify(regnr) bitstr, \
627 .arch_flags = bitnr, \
628 .ops = &sh7722_mstpcr ## regnr ## _clk_ops, \
629}
630
631#define DECLARE_MSTPCR(regnr) \
632 DECLARE_MSTPCRN(regnr, 31, "31"), \
633 DECLARE_MSTPCRN(regnr, 30, "30"), \
634 DECLARE_MSTPCRN(regnr, 29, "29"), \
635 DECLARE_MSTPCRN(regnr, 28, "28"), \
636 DECLARE_MSTPCRN(regnr, 27, "27"), \
637 DECLARE_MSTPCRN(regnr, 26, "26"), \
638 DECLARE_MSTPCRN(regnr, 25, "25"), \
639 DECLARE_MSTPCRN(regnr, 24, "24"), \
640 DECLARE_MSTPCRN(regnr, 23, "23"), \
641 DECLARE_MSTPCRN(regnr, 22, "22"), \
642 DECLARE_MSTPCRN(regnr, 21, "21"), \
643 DECLARE_MSTPCRN(regnr, 20, "20"), \
644 DECLARE_MSTPCRN(regnr, 19, "19"), \
645 DECLARE_MSTPCRN(regnr, 18, "18"), \
646 DECLARE_MSTPCRN(regnr, 17, "17"), \
647 DECLARE_MSTPCRN(regnr, 16, "16"), \
648 DECLARE_MSTPCRN(regnr, 15, "15"), \
649 DECLARE_MSTPCRN(regnr, 14, "14"), \
650 DECLARE_MSTPCRN(regnr, 13, "13"), \
651 DECLARE_MSTPCRN(regnr, 12, "12"), \
652 DECLARE_MSTPCRN(regnr, 11, "11"), \
653 DECLARE_MSTPCRN(regnr, 10, "10"), \
654 DECLARE_MSTPCRN(regnr, 9, "09"), \
655 DECLARE_MSTPCRN(regnr, 8, "08"), \
656 DECLARE_MSTPCRN(regnr, 7, "07"), \
657 DECLARE_MSTPCRN(regnr, 6, "06"), \
658 DECLARE_MSTPCRN(regnr, 5, "05"), \
659 DECLARE_MSTPCRN(regnr, 4, "04"), \
660 DECLARE_MSTPCRN(regnr, 3, "03"), \
661 DECLARE_MSTPCRN(regnr, 2, "02"), \
662 DECLARE_MSTPCRN(regnr, 1, "01"), \
663 DECLARE_MSTPCRN(regnr, 0, "00")
664
665static struct clk sh7722_mstpcr[] = {
666 DECLARE_MSTPCR(0),
667 DECLARE_MSTPCR(1),
668 DECLARE_MSTPCR(2),
669};
670
561static struct clk *sh7722_clocks[] = { 671static struct clk *sh7722_clocks[] = {
562 &sh7722_umem_clock, 672 &sh7722_umem_clock,
563 &sh7722_sh_clock, 673 &sh7722_sh_clock,
@@ -600,5 +710,11 @@ int __init arch_clk_init(void)
600 clk_register(sh7722_clocks[i]); 710 clk_register(sh7722_clocks[i]);
601 } 711 }
602 clk_put(master); 712 clk_put(master);
713
714 for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) {
715 pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name);
716 clk_register(&sh7722_mstpcr[i]);
717 }
718
603 return 0; 719 return 0;
604} 720}