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authorMagnus Damm <damm@igel.co.jp>2007-08-16 11:53:07 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-20 22:57:50 -0400
commit0dc3fc04dd0251aa95b49ca7048e9e8f24291166 (patch)
tree549dc99c3b7548738b02657415c7c5988630da4a /arch/sh
parentc4773bc2a011efa9abe2027f6959106d6f911889 (diff)
sh: intc - add support for sh7619
This patch converts the cpu specific interrupt setup code for sh7619 from ipr to intc. New vectors are also added to match the information provided by the datasheet. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c93
-rw-r--r--arch/sh/mm/Kconfig2
2 files changed, 57 insertions, 38 deletions
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index a979b981e6a3..ec6adc3f306f 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -12,6 +12,61 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <asm/sci.h> 13#include <asm/sci.h>
14 14
15enum {
16 UNUSED = 0,
17
18 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 WDT, EDMAC, CMT0, CMT1,
21 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
22 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
23 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
24 HIF_HIFI, HIF_HIFBI,
25 DMAC0, DMAC1, DMAC2, DMAC3,
26 SIOF,
27
28 /* interrupt groups */
29 SCIF0, SCIF1, SCIF2,
30};
31
32static struct intc_vect vectors[] __initdata = {
33 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
34 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
35 INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
36 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
37 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
38 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
39 INTC_IRQ(SCIF0_ERI, 88), INTC_IRQ(SCIF0_RXI, 89),
40 INTC_IRQ(SCIF0_BRI, 90), INTC_IRQ(SCIF0_TXI, 91),
41 INTC_IRQ(SCIF1_ERI, 92), INTC_IRQ(SCIF1_RXI, 93),
42 INTC_IRQ(SCIF1_BRI, 94), INTC_IRQ(SCIF1_TXI, 95),
43 INTC_IRQ(SCIF2_ERI, 96), INTC_IRQ(SCIF2_RXI, 97),
44 INTC_IRQ(SCIF2_BRI, 98), INTC_IRQ(SCIF2_TXI, 99),
45 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
46 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
47 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
48 INTC_IRQ(SIOF, 108),
49};
50
51static struct intc_group groups[] __initdata = {
52 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
53 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
54 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
55};
56
57static struct intc_prio_reg prio_registers[] __initdata = {
58 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
59 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
60 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
61 { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
62 { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
63 { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
64 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
65};
66
67static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, groups,
68 NULL, NULL, prio_registers, NULL);
69
15static struct plat_sci_port sci_platform_data[] = { 70static struct plat_sci_port sci_platform_data[] = {
16 { 71 {
17 .mapbase = 0xf8400000, 72 .mapbase = 0xf8400000,
@@ -52,43 +107,7 @@ static int __init sh7619_devices_setup(void)
52} 107}
53__initcall(sh7619_devices_setup); 108__initcall(sh7619_devices_setup);
54 109
55static struct ipr_data ipr_irq_table[] = {
56 { 86, 0, 4, 2 }, /* CMI0 */
57 { 88, 1, 12, 3 }, /* SCIF0_ERI */
58 { 89, 1, 12, 3 }, /* SCIF0_RXI */
59 { 90, 1, 12, 3 }, /* SCIF0_BRI */
60 { 91, 1, 12, 3 }, /* SCIF0_TXI */
61 { 92, 1, 8, 3 }, /* SCIF1_ERI */
62 { 93, 1, 8, 3 }, /* SCIF1_RXI */
63 { 94, 1, 8, 3 }, /* SCIF1_BRI */
64 { 95, 1, 8, 3 }, /* SCIF1_TXI */
65 { 96, 1, 4, 3 }, /* SCIF2_ERI */
66 { 97, 1, 4, 3 }, /* SCIF2_RXI */
67 { 98, 1, 4, 3 }, /* SCIF2_BRI */
68 { 99, 1, 4, 3 }, /* SCIF2_TXI */
69};
70
71static unsigned long ipr_offsets[] = {
72 0xf8080000, /* IPRC */
73 0xf8080002, /* IPRD */
74 0xf8080004, /* IPRE */
75 0xf8080006, /* IPRF */
76 0xf8080008, /* IPRG */
77};
78
79static struct ipr_desc ipr_irq_desc = {
80 .ipr_offsets = ipr_offsets,
81 .nr_offsets = ARRAY_SIZE(ipr_offsets),
82
83 .ipr_data = ipr_irq_table,
84 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
85
86 .chip = {
87 .name = "IPR-sh7619",
88 },
89};
90
91void __init plat_irq_setup(void) 110void __init plat_irq_setup(void)
92{ 111{
93 register_ipr_controller(&ipr_irq_desc); 112 register_intc_controller(&intc_desc);
94} 113}
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 5487b99d4f6d..abc032505848 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -50,7 +50,7 @@ choice
50config CPU_SUBTYPE_SH7619 50config CPU_SUBTYPE_SH7619
51 bool "Support SH7619 processor" 51 bool "Support SH7619 processor"
52 select CPU_SH2 52 select CPU_SH2
53 select CPU_HAS_IPR_IRQ 53 select CPU_HAS_INTC_IRQ
54 54
55# SH-2A Processor Support 55# SH-2A Processor Support
56 56