aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2008-10-01 03:13:54 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-10-01 03:13:54 -0400
commitbbfbd8b151fe35c9a1180a7f5254c5d6b8387cc0 (patch)
treee39f364221492d64c7f8fd80c1ceb2065350c4d7 /arch/sh
parent7ff731aeba1cdac473c818a9884eb94ddad18e7f (diff)
sh: Move the shared INTC code out to drivers/sh/
The INTC code will be re-used across different architectures, so move this out to drivers/sh/ and include/linux/sh_intc.h respectively. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/include/asm/hw_irq.h92
-rw-r--r--arch/sh/kernel/cpu/irq/Makefile2
-rw-r--r--arch/sh/kernel/cpu/irq/intc.c712
3 files changed, 2 insertions, 804 deletions
diff --git a/arch/sh/include/asm/hw_irq.h b/arch/sh/include/asm/hw_irq.h
index d557b00111bf..603cdde813d1 100644
--- a/arch/sh/include/asm/hw_irq.h
+++ b/arch/sh/include/asm/hw_irq.h
@@ -2,6 +2,7 @@
2#define __ASM_SH_HW_IRQ_H 2#define __ASM_SH_HW_IRQ_H
3 3
4#include <linux/init.h> 4#include <linux/init.h>
5#include <linux/sh_intc.h>
5#include <asm/atomic.h> 6#include <asm/atomic.h>
6 7
7extern atomic_t irq_err_count; 8extern atomic_t irq_err_count;
@@ -23,101 +24,12 @@ struct ipr_desc {
23 24
24void register_ipr_controller(struct ipr_desc *); 25void register_ipr_controller(struct ipr_desc *);
25 26
26typedef unsigned char intc_enum;
27
28struct intc_vect {
29 intc_enum enum_id;
30 unsigned short vect;
31};
32
33#define INTC_VECT(enum_id, vect) { enum_id, vect }
34#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
35
36struct intc_group {
37 intc_enum enum_id;
38 intc_enum enum_ids[32];
39};
40
41#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
42
43struct intc_mask_reg {
44 unsigned long set_reg, clr_reg, reg_width;
45 intc_enum enum_ids[32];
46#ifdef CONFIG_SMP
47 unsigned long smp;
48#endif
49};
50
51struct intc_prio_reg {
52 unsigned long set_reg, clr_reg, reg_width, field_width;
53 intc_enum enum_ids[16];
54#ifdef CONFIG_SMP
55 unsigned long smp;
56#endif
57};
58
59struct intc_sense_reg {
60 unsigned long reg, reg_width, field_width;
61 intc_enum enum_ids[16];
62};
63
64#ifdef CONFIG_SMP
65#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
66#else
67#define INTC_SMP(stride, nr)
68#endif
69
70struct intc_desc {
71 struct intc_vect *vectors;
72 unsigned int nr_vectors;
73 struct intc_group *groups;
74 unsigned int nr_groups;
75 struct intc_mask_reg *mask_regs;
76 unsigned int nr_mask_regs;
77 struct intc_prio_reg *prio_regs;
78 unsigned int nr_prio_regs;
79 struct intc_sense_reg *sense_regs;
80 unsigned int nr_sense_regs;
81 char *name;
82#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
83 struct intc_mask_reg *ack_regs;
84 unsigned int nr_ack_regs;
85#endif
86};
87
88#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
89#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
90 mask_regs, prio_regs, sense_regs) \
91struct intc_desc symbol __initdata = { \
92 _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
93 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
94 _INTC_ARRAY(sense_regs), \
95 chipname, \
96}
97
98#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
99#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
100 mask_regs, prio_regs, sense_regs, ack_regs) \
101struct intc_desc symbol __initdata = { \
102 _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
103 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
104 _INTC_ARRAY(sense_regs), \
105 chipname, \
106 _INTC_ARRAY(ack_regs), \
107}
108#endif
109
110void __init register_intc_controller(struct intc_desc *desc);
111int intc_set_priority(unsigned int irq, unsigned int prio);
112
113void __init plat_irq_setup(void); 27void __init plat_irq_setup(void);
114#ifdef CONFIG_CPU_SH3
115void __init plat_irq_setup_sh3(void); 28void __init plat_irq_setup_sh3(void);
116#endif 29void __init plat_irq_setup_pins(int mode);
117 30
118enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210, 31enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
119 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK, 32 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
120 IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; 33 IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
121void __init plat_irq_setup_pins(int mode);
122 34
123#endif /* __ASM_SH_HW_IRQ_H */ 35#endif /* __ASM_SH_HW_IRQ_H */
diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile
index 462a8f6dfee2..f0c7025a67d1 100644
--- a/arch/sh/kernel/cpu/irq/Makefile
+++ b/arch/sh/kernel/cpu/irq/Makefile
@@ -1,8 +1,6 @@
1# 1#
2# Makefile for the Linux/SuperH CPU-specifc IRQ handlers. 2# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
3# 3#
4obj-y += intc.o
5
6obj-$(CONFIG_SUPERH32) += imask.o 4obj-$(CONFIG_SUPERH32) += imask.o
7obj-$(CONFIG_CPU_SH5) += intc-sh5.o 5obj-$(CONFIG_CPU_SH5) += intc-sh5.o
8obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o 6obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
deleted file mode 100644
index 138efa4e95db..000000000000
--- a/arch/sh/kernel/cpu/irq/intc.c
+++ /dev/null
@@ -1,712 +0,0 @@
1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/io.h>
22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
24
25#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
26 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
27 ((addr_e) << 16) | ((addr_d << 24)))
28
29#define _INTC_SHIFT(h) (h & 0x1f)
30#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
31#define _INTC_FN(h) ((h >> 9) & 0xf)
32#define _INTC_MODE(h) ((h >> 13) & 0x7)
33#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
34#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
35
36struct intc_handle_int {
37 unsigned int irq;
38 unsigned long handle;
39};
40
41struct intc_desc_int {
42 unsigned long *reg;
43#ifdef CONFIG_SMP
44 unsigned long *smp;
45#endif
46 unsigned int nr_reg;
47 struct intc_handle_int *prio;
48 unsigned int nr_prio;
49 struct intc_handle_int *sense;
50 unsigned int nr_sense;
51 struct irq_chip chip;
52};
53
54#ifdef CONFIG_SMP
55#define IS_SMP(x) x.smp
56#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
57#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
58#else
59#define IS_SMP(x) 0
60#define INTC_REG(d, x, c) (d->reg[(x)])
61#define SMP_NR(d, x) 1
62#endif
63
64static unsigned int intc_prio_level[NR_IRQS]; /* for now */
65#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
66static unsigned long ack_handle[NR_IRQS];
67#endif
68
69static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
70{
71 struct irq_chip *chip = get_irq_chip(irq);
72 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
73}
74
75static inline unsigned int set_field(unsigned int value,
76 unsigned int field_value,
77 unsigned int handle)
78{
79 unsigned int width = _INTC_WIDTH(handle);
80 unsigned int shift = _INTC_SHIFT(handle);
81
82 value &= ~(((1 << width) - 1) << shift);
83 value |= field_value << shift;
84 return value;
85}
86
87static void write_8(unsigned long addr, unsigned long h, unsigned long data)
88{
89 __raw_writeb(set_field(0, data, h), addr);
90}
91
92static void write_16(unsigned long addr, unsigned long h, unsigned long data)
93{
94 __raw_writew(set_field(0, data, h), addr);
95}
96
97static void write_32(unsigned long addr, unsigned long h, unsigned long data)
98{
99 __raw_writel(set_field(0, data, h), addr);
100}
101
102static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
103{
104 unsigned long flags;
105 local_irq_save(flags);
106 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
107 local_irq_restore(flags);
108}
109
110static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
111{
112 unsigned long flags;
113 local_irq_save(flags);
114 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
115 local_irq_restore(flags);
116}
117
118static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
119{
120 unsigned long flags;
121 local_irq_save(flags);
122 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
123 local_irq_restore(flags);
124}
125
126enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
127
128static void (*intc_reg_fns[])(unsigned long addr,
129 unsigned long h,
130 unsigned long data) = {
131 [REG_FN_WRITE_BASE + 0] = write_8,
132 [REG_FN_WRITE_BASE + 1] = write_16,
133 [REG_FN_WRITE_BASE + 3] = write_32,
134 [REG_FN_MODIFY_BASE + 0] = modify_8,
135 [REG_FN_MODIFY_BASE + 1] = modify_16,
136 [REG_FN_MODIFY_BASE + 3] = modify_32,
137};
138
139enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
140 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
141 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
142 MODE_PRIO_REG, /* Priority value written to enable interrupt */
143 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
144};
145
146static void intc_mode_field(unsigned long addr,
147 unsigned long handle,
148 void (*fn)(unsigned long,
149 unsigned long,
150 unsigned long),
151 unsigned int irq)
152{
153 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
154}
155
156static void intc_mode_zero(unsigned long addr,
157 unsigned long handle,
158 void (*fn)(unsigned long,
159 unsigned long,
160 unsigned long),
161 unsigned int irq)
162{
163 fn(addr, handle, 0);
164}
165
166static void intc_mode_prio(unsigned long addr,
167 unsigned long handle,
168 void (*fn)(unsigned long,
169 unsigned long,
170 unsigned long),
171 unsigned int irq)
172{
173 fn(addr, handle, intc_prio_level[irq]);
174}
175
176static void (*intc_enable_fns[])(unsigned long addr,
177 unsigned long handle,
178 void (*fn)(unsigned long,
179 unsigned long,
180 unsigned long),
181 unsigned int irq) = {
182 [MODE_ENABLE_REG] = intc_mode_field,
183 [MODE_MASK_REG] = intc_mode_zero,
184 [MODE_DUAL_REG] = intc_mode_field,
185 [MODE_PRIO_REG] = intc_mode_prio,
186 [MODE_PCLR_REG] = intc_mode_prio,
187};
188
189static void (*intc_disable_fns[])(unsigned long addr,
190 unsigned long handle,
191 void (*fn)(unsigned long,
192 unsigned long,
193 unsigned long),
194 unsigned int irq) = {
195 [MODE_ENABLE_REG] = intc_mode_zero,
196 [MODE_MASK_REG] = intc_mode_field,
197 [MODE_DUAL_REG] = intc_mode_field,
198 [MODE_PRIO_REG] = intc_mode_zero,
199 [MODE_PCLR_REG] = intc_mode_field,
200};
201
202static inline void _intc_enable(unsigned int irq, unsigned long handle)
203{
204 struct intc_desc_int *d = get_intc_desc(irq);
205 unsigned long addr;
206 unsigned int cpu;
207
208 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
209 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
210 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
211 [_INTC_FN(handle)], irq);
212 }
213}
214
215static void intc_enable(unsigned int irq)
216{
217 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
218}
219
220static void intc_disable(unsigned int irq)
221{
222 struct intc_desc_int *d = get_intc_desc(irq);
223 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
224 unsigned long addr;
225 unsigned int cpu;
226
227 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
228 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
229 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
230 [_INTC_FN(handle)], irq);
231 }
232}
233
234#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
235static void intc_mask_ack(unsigned int irq)
236{
237 struct intc_desc_int *d = get_intc_desc(irq);
238 unsigned long handle = ack_handle[irq];
239 unsigned long addr;
240
241 intc_disable(irq);
242
243 /* read register and write zero only to the assocaited bit */
244
245 if (handle) {
246 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
247 switch (_INTC_FN(handle)) {
248 case REG_FN_MODIFY_BASE + 0: /* 8bit */
249 __raw_readb(addr);
250 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
251 break;
252 case REG_FN_MODIFY_BASE + 1: /* 16bit */
253 __raw_readw(addr);
254 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
255 break;
256 case REG_FN_MODIFY_BASE + 3: /* 32bit */
257 __raw_readl(addr);
258 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
259 break;
260 default:
261 BUG();
262 break;
263 }
264 }
265}
266#endif
267
268static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
269 unsigned int nr_hp,
270 unsigned int irq)
271{
272 int i;
273
274 /* this doesn't scale well, but...
275 *
276 * this function should only be used for cerain uncommon
277 * operations such as intc_set_priority() and intc_set_sense()
278 * and in those rare cases performance doesn't matter that much.
279 * keeping the memory footprint low is more important.
280 *
281 * one rather simple way to speed this up and still keep the
282 * memory footprint down is to make sure the array is sorted
283 * and then perform a bisect to lookup the irq.
284 */
285
286 for (i = 0; i < nr_hp; i++) {
287 if ((hp + i)->irq != irq)
288 continue;
289
290 return hp + i;
291 }
292
293 return NULL;
294}
295
296int intc_set_priority(unsigned int irq, unsigned int prio)
297{
298 struct intc_desc_int *d = get_intc_desc(irq);
299 struct intc_handle_int *ihp;
300
301 if (!intc_prio_level[irq] || prio <= 1)
302 return -EINVAL;
303
304 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
305 if (ihp) {
306 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
307 return -EINVAL;
308
309 intc_prio_level[irq] = prio;
310
311 /*
312 * only set secondary masking method directly
313 * primary masking method is using intc_prio_level[irq]
314 * priority level will be set during next enable()
315 */
316
317 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
318 _intc_enable(irq, ihp->handle);
319 }
320 return 0;
321}
322
323#define VALID(x) (x | 0x80)
324
325static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
326 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
327 [IRQ_TYPE_EDGE_RISING] = VALID(1),
328 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
329 /* SH7706, SH7707 and SH7709 do not support high level triggered */
330#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
331 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
332 !defined(CONFIG_CPU_SUBTYPE_SH7709)
333 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
334#endif
335};
336
337static int intc_set_sense(unsigned int irq, unsigned int type)
338{
339 struct intc_desc_int *d = get_intc_desc(irq);
340 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
341 struct intc_handle_int *ihp;
342 unsigned long addr;
343
344 if (!value)
345 return -EINVAL;
346
347 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
348 if (ihp) {
349 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
350 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
351 }
352 return 0;
353}
354
355static unsigned int __init intc_get_reg(struct intc_desc_int *d,
356 unsigned long address)
357{
358 unsigned int k;
359
360 for (k = 0; k < d->nr_reg; k++) {
361 if (d->reg[k] == address)
362 return k;
363 }
364
365 BUG();
366 return 0;
367}
368
369static intc_enum __init intc_grp_id(struct intc_desc *desc,
370 intc_enum enum_id)
371{
372 struct intc_group *g = desc->groups;
373 unsigned int i, j;
374
375 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
376 g = desc->groups + i;
377
378 for (j = 0; g->enum_ids[j]; j++) {
379 if (g->enum_ids[j] != enum_id)
380 continue;
381
382 return g->enum_id;
383 }
384 }
385
386 return 0;
387}
388
389static unsigned int __init intc_mask_data(struct intc_desc *desc,
390 struct intc_desc_int *d,
391 intc_enum enum_id, int do_grps)
392{
393 struct intc_mask_reg *mr = desc->mask_regs;
394 unsigned int i, j, fn, mode;
395 unsigned long reg_e, reg_d;
396
397 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
398 mr = desc->mask_regs + i;
399
400 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
401 if (mr->enum_ids[j] != enum_id)
402 continue;
403
404 if (mr->set_reg && mr->clr_reg) {
405 fn = REG_FN_WRITE_BASE;
406 mode = MODE_DUAL_REG;
407 reg_e = mr->clr_reg;
408 reg_d = mr->set_reg;
409 } else {
410 fn = REG_FN_MODIFY_BASE;
411 if (mr->set_reg) {
412 mode = MODE_ENABLE_REG;
413 reg_e = mr->set_reg;
414 reg_d = mr->set_reg;
415 } else {
416 mode = MODE_MASK_REG;
417 reg_e = mr->clr_reg;
418 reg_d = mr->clr_reg;
419 }
420 }
421
422 fn += (mr->reg_width >> 3) - 1;
423 return _INTC_MK(fn, mode,
424 intc_get_reg(d, reg_e),
425 intc_get_reg(d, reg_d),
426 1,
427 (mr->reg_width - 1) - j);
428 }
429 }
430
431 if (do_grps)
432 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
433
434 return 0;
435}
436
437static unsigned int __init intc_prio_data(struct intc_desc *desc,
438 struct intc_desc_int *d,
439 intc_enum enum_id, int do_grps)
440{
441 struct intc_prio_reg *pr = desc->prio_regs;
442 unsigned int i, j, fn, mode, bit;
443 unsigned long reg_e, reg_d;
444
445 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
446 pr = desc->prio_regs + i;
447
448 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
449 if (pr->enum_ids[j] != enum_id)
450 continue;
451
452 if (pr->set_reg && pr->clr_reg) {
453 fn = REG_FN_WRITE_BASE;
454 mode = MODE_PCLR_REG;
455 reg_e = pr->set_reg;
456 reg_d = pr->clr_reg;
457 } else {
458 fn = REG_FN_MODIFY_BASE;
459 mode = MODE_PRIO_REG;
460 if (!pr->set_reg)
461 BUG();
462 reg_e = pr->set_reg;
463 reg_d = pr->set_reg;
464 }
465
466 fn += (pr->reg_width >> 3) - 1;
467
468 BUG_ON((j + 1) * pr->field_width > pr->reg_width);
469
470 bit = pr->reg_width - ((j + 1) * pr->field_width);
471
472 return _INTC_MK(fn, mode,
473 intc_get_reg(d, reg_e),
474 intc_get_reg(d, reg_d),
475 pr->field_width, bit);
476 }
477 }
478
479 if (do_grps)
480 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
481
482 return 0;
483}
484
485#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
486static unsigned int __init intc_ack_data(struct intc_desc *desc,
487 struct intc_desc_int *d,
488 intc_enum enum_id)
489{
490 struct intc_mask_reg *mr = desc->ack_regs;
491 unsigned int i, j, fn, mode;
492 unsigned long reg_e, reg_d;
493
494 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
495 mr = desc->ack_regs + i;
496
497 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
498 if (mr->enum_ids[j] != enum_id)
499 continue;
500
501 fn = REG_FN_MODIFY_BASE;
502 mode = MODE_ENABLE_REG;
503 reg_e = mr->set_reg;
504 reg_d = mr->set_reg;
505
506 fn += (mr->reg_width >> 3) - 1;
507 return _INTC_MK(fn, mode,
508 intc_get_reg(d, reg_e),
509 intc_get_reg(d, reg_d),
510 1,
511 (mr->reg_width - 1) - j);
512 }
513 }
514
515 return 0;
516}
517#endif
518
519static unsigned int __init intc_sense_data(struct intc_desc *desc,
520 struct intc_desc_int *d,
521 intc_enum enum_id)
522{
523 struct intc_sense_reg *sr = desc->sense_regs;
524 unsigned int i, j, fn, bit;
525
526 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
527 sr = desc->sense_regs + i;
528
529 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
530 if (sr->enum_ids[j] != enum_id)
531 continue;
532
533 fn = REG_FN_MODIFY_BASE;
534 fn += (sr->reg_width >> 3) - 1;
535
536 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
537
538 bit = sr->reg_width - ((j + 1) * sr->field_width);
539
540 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
541 0, sr->field_width, bit);
542 }
543 }
544
545 return 0;
546}
547
548static void __init intc_register_irq(struct intc_desc *desc,
549 struct intc_desc_int *d,
550 intc_enum enum_id,
551 unsigned int irq)
552{
553 struct intc_handle_int *hp;
554 unsigned int data[2], primary;
555
556 /* Prefer single interrupt source bitmap over other combinations:
557 * 1. bitmap, single interrupt source
558 * 2. priority, single interrupt source
559 * 3. bitmap, multiple interrupt sources (groups)
560 * 4. priority, multiple interrupt sources (groups)
561 */
562
563 data[0] = intc_mask_data(desc, d, enum_id, 0);
564 data[1] = intc_prio_data(desc, d, enum_id, 0);
565
566 primary = 0;
567 if (!data[0] && data[1])
568 primary = 1;
569
570 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
571 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
572
573 if (!data[primary])
574 primary ^= 1;
575
576 BUG_ON(!data[primary]); /* must have primary masking method */
577
578 disable_irq_nosync(irq);
579 set_irq_chip_and_handler_name(irq, &d->chip,
580 handle_level_irq, "level");
581 set_irq_chip_data(irq, (void *)data[primary]);
582
583 /* set priority level
584 * - this needs to be at least 2 for 5-bit priorities on 7780
585 */
586 intc_prio_level[irq] = 2;
587
588 /* enable secondary masking method if present */
589 if (data[!primary])
590 _intc_enable(irq, data[!primary]);
591
592 /* add irq to d->prio list if priority is available */
593 if (data[1]) {
594 hp = d->prio + d->nr_prio;
595 hp->irq = irq;
596 hp->handle = data[1];
597
598 if (primary) {
599 /*
600 * only secondary priority should access registers, so
601 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
602 */
603
604 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
605 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
606 }
607 d->nr_prio++;
608 }
609
610 /* add irq to d->sense list if sense is available */
611 data[0] = intc_sense_data(desc, d, enum_id);
612 if (data[0]) {
613 (d->sense + d->nr_sense)->irq = irq;
614 (d->sense + d->nr_sense)->handle = data[0];
615 d->nr_sense++;
616 }
617
618 /* irq should be disabled by default */
619 d->chip.mask(irq);
620
621#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
622 if (desc->ack_regs)
623 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
624#endif
625}
626
627static unsigned int __init save_reg(struct intc_desc_int *d,
628 unsigned int cnt,
629 unsigned long value,
630 unsigned int smp)
631{
632 if (value) {
633 d->reg[cnt] = value;
634#ifdef CONFIG_SMP
635 d->smp[cnt] = smp;
636#endif
637 return 1;
638 }
639
640 return 0;
641}
642
643
644void __init register_intc_controller(struct intc_desc *desc)
645{
646 unsigned int i, k, smp;
647 struct intc_desc_int *d;
648
649 d = alloc_bootmem(sizeof(*d));
650
651 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
652 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
653 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
654
655#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
656 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
657#endif
658 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
659#ifdef CONFIG_SMP
660 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
661#endif
662 k = 0;
663
664 if (desc->mask_regs) {
665 for (i = 0; i < desc->nr_mask_regs; i++) {
666 smp = IS_SMP(desc->mask_regs[i]);
667 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
668 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
669 }
670 }
671
672 if (desc->prio_regs) {
673 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
674
675 for (i = 0; i < desc->nr_prio_regs; i++) {
676 smp = IS_SMP(desc->prio_regs[i]);
677 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
678 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
679 }
680 }
681
682 if (desc->sense_regs) {
683 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
684
685 for (i = 0; i < desc->nr_sense_regs; i++) {
686 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
687 }
688 }
689
690 d->chip.name = desc->name;
691 d->chip.mask = intc_disable;
692 d->chip.unmask = intc_enable;
693 d->chip.mask_ack = intc_disable;
694 d->chip.set_type = intc_set_sense;
695
696#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
697 if (desc->ack_regs) {
698 for (i = 0; i < desc->nr_ack_regs; i++)
699 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
700
701 d->chip.mask_ack = intc_mask_ack;
702 }
703#endif
704
705 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
706
707 for (i = 0; i < desc->nr_vectors; i++) {
708 struct intc_vect *vect = desc->vectors + i;
709
710 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
711 }
712}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 18:43:43 -0500