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authorPaul Mundt <lethal@linux-sh.org>2009-03-06 05:20:48 -0500
committerPaul Mundt <lethal@linux-sh.org>2009-03-06 05:20:48 -0500
commit56d604defa91684509ac842317ea14501f224299 (patch)
tree88d0892ab429a3916dfd60b5655234b7f78d71e1 /arch/sh
parent0caedb02c4a02b6fd0f1a62dfeb917353d3c6162 (diff)
sh: multiple vectors per irq - sh7710.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c69
1 files changed, 21 insertions, 48 deletions
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 77eee481de47..335098b66e2f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH3 Setup code for SH7710, SH7712 2 * SH3 Setup code for SH7710, SH7712
3 * 3 *
4 * Copyright (C) 2006, 2007 Paul Mundt 4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu 5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -20,59 +20,40 @@ enum {
20 20
21 /* interrupt sources */ 21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 23 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC,
24 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
25 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
26 DMAC_DEI4, DMAC_DEI5,
27 IPSEC,
28 EDMAC0, EDMAC1, EDMAC2, 24 EDMAC0, EDMAC1, EDMAC2,
29 SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI, 25 SIOF0, SIOF1,
30 SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
31 TMU0, TMU1, TMU2,
32 RTC_ATI, RTC_PRI, RTC_CUI,
33 WDT,
34 REF,
35 26
36 /* interrupt groups */ 27 TMU0, TMU1, TMU2,
37 RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1, 28 RTC, WDT, REF,
38}; 29};
39 30
40static struct intc_vect vectors[] __initdata = { 31static struct intc_vect vectors[] __initdata = {
41 /* IRQ0->5 are handled in setup-sh3.c */ 32 /* IRQ0->5 are handled in setup-sh3.c */
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
45 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
46 INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920), 37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
47 INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960), 38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
48 INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0), 39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
49#ifdef CONFIG_CPU_SUBTYPE_SH7710 40#ifdef CONFIG_CPU_SUBTYPE_SH7710
50 INTC_VECT(IPSEC, 0xbe0), 41 INTC_VECT(IPSEC, 0xbe0),
51#endif 42#endif
52 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
53 INTC_VECT(EDMAC2, 0xc40), 44 INTC_VECT(EDMAC2, 0xc40),
54 INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20), 45 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20),
55 INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60), 46 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60),
56 INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0), 47 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0),
57 INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0), 48 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0),
58 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 49 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
59 INTC_VECT(TMU2, 0x440), 50 INTC_VECT(TMU2, 0x440),
60 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 51 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
61 INTC_VECT(RTC_CUI, 0x4c0), 52 INTC_VECT(RTC, 0x4c0),
62 INTC_VECT(WDT, 0x560), 53 INTC_VECT(WDT, 0x560),
63 INTC_VECT(REF, 0x580), 54 INTC_VECT(REF, 0x580),
64}; 55};
65 56
66static struct intc_group groups[] __initdata = {
67 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
68 INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
69 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
70 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
71 INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
72 INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
73 INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
74};
75
76static struct intc_prio_reg prio_registers[] __initdata = { 57static struct intc_prio_reg prio_registers[] __initdata = {
77 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 58 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
78 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 59 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
@@ -85,7 +66,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
85 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 66 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
86}; 67};
87 68
88static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, 69static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL,
89 NULL, prio_registers, NULL); 70 NULL, prio_registers, NULL);
90 71
91static struct resource rtc_resources[] = { 72static struct resource rtc_resources[] = {
@@ -98,14 +79,6 @@ static struct resource rtc_resources[] = {
98 .start = 20, 79 .start = 20,
99 .flags = IORESOURCE_IRQ, 80 .flags = IORESOURCE_IRQ,
100 }, 81 },
101 [2] = {
102 .start = 21,
103 .flags = IORESOURCE_IRQ,
104 },
105 [3] = {
106 .start = 22,
107 .flags = IORESOURCE_IRQ,
108 },
109}; 82};
110 83
111static struct sh_rtc_platform_info rtc_info = { 84static struct sh_rtc_platform_info rtc_info = {
@@ -127,12 +100,12 @@ static struct plat_sci_port sci_platform_data[] = {
127 .mapbase = 0xa4400000, 100 .mapbase = 0xa4400000,
128 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
129 .type = PORT_SCIF, 102 .type = PORT_SCIF,
130 .irqs = { 52, 53, 55, 54 }, 103 .irqs = { 52, 52, 52, 52 },
131 }, { 104 }, {
132 .mapbase = 0xa4410000, 105 .mapbase = 0xa4410000,
133 .flags = UPF_BOOT_AUTOCONF, 106 .flags = UPF_BOOT_AUTOCONF,
134 .type = PORT_SCIF, 107 .type = PORT_SCIF,
135 .irqs = { 56, 57, 59, 58 }, 108 .irqs = { 56, 56, 56, 56 },
136 }, { 109 }, {
137 110
138 .flags = 0, 111 .flags = 0,