diff options
author | Paul Mundt <lethal@linux-sh.org> | 2006-01-17 01:14:09 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-17 02:15:27 -0500 |
commit | 0d831770b154a057562236e8cf50905c8f1ae1b0 (patch) | |
tree | dc25902b29b09838f2fe32e47be53c951a2fa67e /arch/sh | |
parent | 0025835cf20e07056b8521b8c1d7d0bfe07e81f1 (diff) |
[PATCH] sh: DMA updates
This extends the current SH DMA API somewhat to support a proper virtual
channel abstraction, and also works to represent this through the driver model
by giving each DMAC its own platform device.
There's also a few other minor changes to support a few new CPU subtypes, and
make TEI generation for the SH DMAC configurable.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/sh')
-rw-r--r-- | arch/sh/drivers/dma/dma-api.c | 51 | ||||
-rw-r--r-- | arch/sh/drivers/dma/dma-g2.c | 3 | ||||
-rw-r--r-- | arch/sh/drivers/dma/dma-isa.c | 20 | ||||
-rw-r--r-- | arch/sh/drivers/dma/dma-pvr2.c | 3 | ||||
-rw-r--r-- | arch/sh/drivers/dma/dma-sh.c | 134 | ||||
-rw-r--r-- | arch/sh/drivers/dma/dma-sh.h | 44 | ||||
-rw-r--r-- | arch/sh/drivers/dma/dma-sysfs.c | 31 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/bus.c | 2 |
8 files changed, 194 insertions, 94 deletions
diff --git a/arch/sh/drivers/dma/dma-api.c b/arch/sh/drivers/dma/dma-api.c index 96e3036ec2bb..47c3e837599b 100644 --- a/arch/sh/drivers/dma/dma-api.c +++ b/arch/sh/drivers/dma/dma-api.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * SuperH-specific DMA management API | 4 | * SuperH-specific DMA management API |
5 | * | 5 | * |
6 | * Copyright (C) 2003, 2004 Paul Mundt | 6 | * Copyright (C) 2003, 2004, 2005 Paul Mundt |
7 | * | 7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | 8 | * This file is subject to the terms and conditions of the GNU General Public |
9 | * License. See the file "COPYING" in the main directory of this archive | 9 | * License. See the file "COPYING" in the main directory of this archive |
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/spinlock.h> | 15 | #include <linux/spinlock.h> |
16 | #include <linux/proc_fs.h> | 16 | #include <linux/proc_fs.h> |
17 | #include <linux/list.h> | 17 | #include <linux/list.h> |
18 | #include <linux/platform_device.h> | ||
18 | #include <asm/dma.h> | 19 | #include <asm/dma.h> |
19 | 20 | ||
20 | DEFINE_SPINLOCK(dma_spin_lock); | 21 | DEFINE_SPINLOCK(dma_spin_lock); |
@@ -55,16 +56,14 @@ static LIST_HEAD(registered_dmac_list); | |||
55 | 56 | ||
56 | struct dma_info *get_dma_info(unsigned int chan) | 57 | struct dma_info *get_dma_info(unsigned int chan) |
57 | { | 58 | { |
58 | struct list_head *pos, *tmp; | 59 | struct dma_info *info; |
59 | unsigned int total = 0; | 60 | unsigned int total = 0; |
60 | 61 | ||
61 | /* | 62 | /* |
62 | * Look for each DMAC's range to determine who the owner of | 63 | * Look for each DMAC's range to determine who the owner of |
63 | * the channel is. | 64 | * the channel is. |
64 | */ | 65 | */ |
65 | list_for_each_safe(pos, tmp, ®istered_dmac_list) { | 66 | list_for_each_entry(info, ®istered_dmac_list, list) { |
66 | struct dma_info *info = list_entry(pos, struct dma_info, list); | ||
67 | |||
68 | total += info->nr_channels; | 67 | total += info->nr_channels; |
69 | if (chan > total) | 68 | if (chan > total) |
70 | continue; | 69 | continue; |
@@ -75,6 +74,20 @@ struct dma_info *get_dma_info(unsigned int chan) | |||
75 | return NULL; | 74 | return NULL; |
76 | } | 75 | } |
77 | 76 | ||
77 | static unsigned int get_nr_channels(void) | ||
78 | { | ||
79 | struct dma_info *info; | ||
80 | unsigned int nr = 0; | ||
81 | |||
82 | if (unlikely(list_empty(®istered_dmac_list))) | ||
83 | return nr; | ||
84 | |||
85 | list_for_each_entry(info, ®istered_dmac_list, list) | ||
86 | nr += info->nr_channels; | ||
87 | |||
88 | return nr; | ||
89 | } | ||
90 | |||
78 | struct dma_channel *get_dma_channel(unsigned int chan) | 91 | struct dma_channel *get_dma_channel(unsigned int chan) |
79 | { | 92 | { |
80 | struct dma_info *info = get_dma_info(chan); | 93 | struct dma_info *info = get_dma_info(chan); |
@@ -173,7 +186,7 @@ int dma_xfer(unsigned int chan, unsigned long from, | |||
173 | static int dma_read_proc(char *buf, char **start, off_t off, | 186 | static int dma_read_proc(char *buf, char **start, off_t off, |
174 | int len, int *eof, void *data) | 187 | int len, int *eof, void *data) |
175 | { | 188 | { |
176 | struct list_head *pos, *tmp; | 189 | struct dma_info *info; |
177 | char *p = buf; | 190 | char *p = buf; |
178 | 191 | ||
179 | if (list_empty(®istered_dmac_list)) | 192 | if (list_empty(®istered_dmac_list)) |
@@ -182,8 +195,7 @@ static int dma_read_proc(char *buf, char **start, off_t off, | |||
182 | /* | 195 | /* |
183 | * Iterate over each registered DMAC | 196 | * Iterate over each registered DMAC |
184 | */ | 197 | */ |
185 | list_for_each_safe(pos, tmp, ®istered_dmac_list) { | 198 | list_for_each_entry(info, ®istered_dmac_list, list) { |
186 | struct dma_info *info = list_entry(pos, struct dma_info, list); | ||
187 | int i; | 199 | int i; |
188 | 200 | ||
189 | /* | 201 | /* |
@@ -205,9 +217,9 @@ static int dma_read_proc(char *buf, char **start, off_t off, | |||
205 | #endif | 217 | #endif |
206 | 218 | ||
207 | 219 | ||
208 | int __init register_dmac(struct dma_info *info) | 220 | int register_dmac(struct dma_info *info) |
209 | { | 221 | { |
210 | int i; | 222 | unsigned int total_channels, i; |
211 | 223 | ||
212 | INIT_LIST_HEAD(&info->list); | 224 | INIT_LIST_HEAD(&info->list); |
213 | 225 | ||
@@ -217,6 +229,11 @@ int __init register_dmac(struct dma_info *info) | |||
217 | 229 | ||
218 | BUG_ON((info->flags & DMAC_CHANNELS_CONFIGURED) && !info->channels); | 230 | BUG_ON((info->flags & DMAC_CHANNELS_CONFIGURED) && !info->channels); |
219 | 231 | ||
232 | info->pdev = platform_device_register_simple((char *)info->name, -1, | ||
233 | NULL, 0); | ||
234 | if (IS_ERR(info->pdev)) | ||
235 | return PTR_ERR(info->pdev); | ||
236 | |||
220 | /* | 237 | /* |
221 | * Don't touch pre-configured channels | 238 | * Don't touch pre-configured channels |
222 | */ | 239 | */ |
@@ -232,10 +249,12 @@ int __init register_dmac(struct dma_info *info) | |||
232 | memset(info->channels, 0, size); | 249 | memset(info->channels, 0, size); |
233 | } | 250 | } |
234 | 251 | ||
252 | total_channels = get_nr_channels(); | ||
235 | for (i = 0; i < info->nr_channels; i++) { | 253 | for (i = 0; i < info->nr_channels; i++) { |
236 | struct dma_channel *chan = info->channels + i; | 254 | struct dma_channel *chan = info->channels + i; |
237 | 255 | ||
238 | chan->chan = i; | 256 | chan->chan = i; |
257 | chan->vchan = i + total_channels; | ||
239 | 258 | ||
240 | memcpy(chan->dev_id, "Unused", 7); | 259 | memcpy(chan->dev_id, "Unused", 7); |
241 | 260 | ||
@@ -245,9 +264,7 @@ int __init register_dmac(struct dma_info *info) | |||
245 | init_MUTEX(&chan->sem); | 264 | init_MUTEX(&chan->sem); |
246 | init_waitqueue_head(&chan->wait_queue); | 265 | init_waitqueue_head(&chan->wait_queue); |
247 | 266 | ||
248 | #ifdef CONFIG_SYSFS | 267 | dma_create_sysfs_files(chan, info); |
249 | dma_create_sysfs_files(chan); | ||
250 | #endif | ||
251 | } | 268 | } |
252 | 269 | ||
253 | list_add(&info->list, ®istered_dmac_list); | 270 | list_add(&info->list, ®istered_dmac_list); |
@@ -255,12 +272,18 @@ int __init register_dmac(struct dma_info *info) | |||
255 | return 0; | 272 | return 0; |
256 | } | 273 | } |
257 | 274 | ||
258 | void __exit unregister_dmac(struct dma_info *info) | 275 | void unregister_dmac(struct dma_info *info) |
259 | { | 276 | { |
277 | unsigned int i; | ||
278 | |||
279 | for (i = 0; i < info->nr_channels; i++) | ||
280 | dma_remove_sysfs_files(info->channels + i, info); | ||
281 | |||
260 | if (!(info->flags & DMAC_CHANNELS_CONFIGURED)) | 282 | if (!(info->flags & DMAC_CHANNELS_CONFIGURED)) |
261 | kfree(info->channels); | 283 | kfree(info->channels); |
262 | 284 | ||
263 | list_del(&info->list); | 285 | list_del(&info->list); |
286 | platform_device_unregister(info->pdev); | ||
264 | } | 287 | } |
265 | 288 | ||
266 | static int __init dma_api_init(void) | 289 | static int __init dma_api_init(void) |
diff --git a/arch/sh/drivers/dma/dma-g2.c b/arch/sh/drivers/dma/dma-g2.c index 231e3f6fb28f..5afab6f56ec3 100644 --- a/arch/sh/drivers/dma/dma-g2.c +++ b/arch/sh/drivers/dma/dma-g2.c | |||
@@ -140,7 +140,7 @@ static struct dma_ops g2_dma_ops = { | |||
140 | }; | 140 | }; |
141 | 141 | ||
142 | static struct dma_info g2_dma_info = { | 142 | static struct dma_info g2_dma_info = { |
143 | .name = "G2 DMA", | 143 | .name = "g2_dmac", |
144 | .nr_channels = 4, | 144 | .nr_channels = 4, |
145 | .ops = &g2_dma_ops, | 145 | .ops = &g2_dma_ops, |
146 | .flags = DMAC_CHANNELS_TEI_CAPABLE, | 146 | .flags = DMAC_CHANNELS_TEI_CAPABLE, |
@@ -160,6 +160,7 @@ static int __init g2_dma_init(void) | |||
160 | static void __exit g2_dma_exit(void) | 160 | static void __exit g2_dma_exit(void) |
161 | { | 161 | { |
162 | free_irq(HW_EVENT_G2_DMA, 0); | 162 | free_irq(HW_EVENT_G2_DMA, 0); |
163 | unregister_dmac(&g2_dma_info); | ||
163 | } | 164 | } |
164 | 165 | ||
165 | subsys_initcall(g2_dma_init); | 166 | subsys_initcall(g2_dma_init); |
diff --git a/arch/sh/drivers/dma/dma-isa.c b/arch/sh/drivers/dma/dma-isa.c index 1c9bc45b8bcb..05a74ffdb68d 100644 --- a/arch/sh/drivers/dma/dma-isa.c +++ b/arch/sh/drivers/dma/dma-isa.c | |||
@@ -25,14 +25,14 @@ | |||
25 | * such, this code is meant for only the simplest of tasks (and shouldn't be | 25 | * such, this code is meant for only the simplest of tasks (and shouldn't be |
26 | * used in any new drivers at all). | 26 | * used in any new drivers at all). |
27 | * | 27 | * |
28 | * It should also be noted that various functions here are labelled as | 28 | * NOTE: ops->xfer() is the preferred way of doing things. However, there |
29 | * being deprecated. This is due to the fact that the ops->xfer() method is | 29 | * are some users of the ISA DMA API that exist in common code that we |
30 | * the preferred way of doing things (as well as just grabbing the spinlock | 30 | * don't necessarily want to go out of our way to break, so we still |
31 | * directly). As such, any users of this interface will be warned rather | 31 | * allow for some compatability at that level. Any new code is strongly |
32 | * loudly. | 32 | * advised to run far away from the ISA DMA API and use the SH DMA API |
33 | * directly. | ||
33 | */ | 34 | */ |
34 | 35 | unsigned long claim_dma_lock(void) | |
35 | unsigned long __deprecated claim_dma_lock(void) | ||
36 | { | 36 | { |
37 | unsigned long flags; | 37 | unsigned long flags; |
38 | 38 | ||
@@ -42,19 +42,19 @@ unsigned long __deprecated claim_dma_lock(void) | |||
42 | } | 42 | } |
43 | EXPORT_SYMBOL(claim_dma_lock); | 43 | EXPORT_SYMBOL(claim_dma_lock); |
44 | 44 | ||
45 | void __deprecated release_dma_lock(unsigned long flags) | 45 | void release_dma_lock(unsigned long flags) |
46 | { | 46 | { |
47 | spin_unlock_irqrestore(&dma_spin_lock, flags); | 47 | spin_unlock_irqrestore(&dma_spin_lock, flags); |
48 | } | 48 | } |
49 | EXPORT_SYMBOL(release_dma_lock); | 49 | EXPORT_SYMBOL(release_dma_lock); |
50 | 50 | ||
51 | void __deprecated disable_dma(unsigned int chan) | 51 | void disable_dma(unsigned int chan) |
52 | { | 52 | { |
53 | /* Nothing */ | 53 | /* Nothing */ |
54 | } | 54 | } |
55 | EXPORT_SYMBOL(disable_dma); | 55 | EXPORT_SYMBOL(disable_dma); |
56 | 56 | ||
57 | void __deprecated enable_dma(unsigned int chan) | 57 | void enable_dma(unsigned int chan) |
58 | { | 58 | { |
59 | struct dma_info *info = get_dma_info(chan); | 59 | struct dma_info *info = get_dma_info(chan); |
60 | struct dma_channel *channel = &info->channels[chan]; | 60 | struct dma_channel *channel = &info->channels[chan]; |
diff --git a/arch/sh/drivers/dma/dma-pvr2.c b/arch/sh/drivers/dma/dma-pvr2.c index 2e1d58f2d1b9..df604975ccc8 100644 --- a/arch/sh/drivers/dma/dma-pvr2.c +++ b/arch/sh/drivers/dma/dma-pvr2.c | |||
@@ -80,7 +80,7 @@ static struct dma_ops pvr2_dma_ops = { | |||
80 | }; | 80 | }; |
81 | 81 | ||
82 | static struct dma_info pvr2_dma_info = { | 82 | static struct dma_info pvr2_dma_info = { |
83 | .name = "PowerVR 2 DMA", | 83 | .name = "pvr2_dmac", |
84 | .nr_channels = 1, | 84 | .nr_channels = 1, |
85 | .ops = &pvr2_dma_ops, | 85 | .ops = &pvr2_dma_ops, |
86 | .flags = DMAC_CHANNELS_TEI_CAPABLE, | 86 | .flags = DMAC_CHANNELS_TEI_CAPABLE, |
@@ -98,6 +98,7 @@ static void __exit pvr2_dma_exit(void) | |||
98 | { | 98 | { |
99 | free_dma(PVR2_CASCADE_CHAN); | 99 | free_dma(PVR2_CASCADE_CHAN); |
100 | free_irq(HW_EVENT_PVR2_DMA, 0); | 100 | free_irq(HW_EVENT_PVR2_DMA, 0); |
101 | unregister_dmac(&pvr2_dma_info); | ||
101 | } | 102 | } |
102 | 103 | ||
103 | subsys_initcall(pvr2_dma_init); | 104 | subsys_initcall(pvr2_dma_init); |
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index 31dacd4444b2..cca26c4c9d1b 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c | |||
@@ -5,6 +5,7 @@ | |||
5 | * | 5 | * |
6 | * Copyright (C) 2000 Takashi YOSHII | 6 | * Copyright (C) 2000 Takashi YOSHII |
7 | * Copyright (C) 2003, 2004 Paul Mundt | 7 | * Copyright (C) 2003, 2004 Paul Mundt |
8 | * Copyright (C) 2005 Andriy Skulysh | ||
8 | * | 9 | * |
9 | * This file is subject to the terms and conditions of the GNU General Public | 10 | * This file is subject to the terms and conditions of the GNU General Public |
10 | * License. See the file "COPYING" in the main directory of this archive | 11 | * License. See the file "COPYING" in the main directory of this archive |
@@ -16,51 +17,28 @@ | |||
16 | #include <linux/irq.h> | 17 | #include <linux/irq.h> |
17 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
18 | #include <linux/module.h> | 19 | #include <linux/module.h> |
20 | #include <asm/dreamcast/dma.h> | ||
19 | #include <asm/signal.h> | 21 | #include <asm/signal.h> |
20 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
21 | #include <asm/dma.h> | 23 | #include <asm/dma.h> |
22 | #include <asm/io.h> | 24 | #include <asm/io.h> |
23 | #include "dma-sh.h" | 25 | #include "dma-sh.h" |
24 | 26 | ||
25 | /* | ||
26 | * The SuperH DMAC supports a number of transmit sizes, we list them here, | ||
27 | * with their respective values as they appear in the CHCR registers. | ||
28 | * | ||
29 | * Defaults to a 64-bit transfer size. | ||
30 | */ | ||
31 | enum { | ||
32 | XMIT_SZ_64BIT, | ||
33 | XMIT_SZ_8BIT, | ||
34 | XMIT_SZ_16BIT, | ||
35 | XMIT_SZ_32BIT, | ||
36 | XMIT_SZ_256BIT, | ||
37 | }; | ||
38 | |||
39 | /* | ||
40 | * The DMA count is defined as the number of bytes to transfer. | ||
41 | */ | ||
42 | static unsigned int ts_shift[] = { | ||
43 | [XMIT_SZ_64BIT] = 3, | ||
44 | [XMIT_SZ_8BIT] = 0, | ||
45 | [XMIT_SZ_16BIT] = 1, | ||
46 | [XMIT_SZ_32BIT] = 2, | ||
47 | [XMIT_SZ_256BIT] = 5, | ||
48 | }; | ||
49 | |||
50 | static inline unsigned int get_dmte_irq(unsigned int chan) | 27 | static inline unsigned int get_dmte_irq(unsigned int chan) |
51 | { | 28 | { |
52 | unsigned int irq; | 29 | unsigned int irq = 0; |
53 | 30 | ||
54 | /* | 31 | /* |
55 | * Normally we could just do DMTE0_IRQ + chan outright, though in the | 32 | * Normally we could just do DMTE0_IRQ + chan outright, though in the |
56 | * case of the 7751R, the DMTE IRQs for channels > 4 start right above | 33 | * case of the 7751R, the DMTE IRQs for channels > 4 start right above |
57 | * the SCIF | 34 | * the SCIF |
58 | */ | 35 | */ |
59 | |||
60 | if (chan < 4) { | 36 | if (chan < 4) { |
61 | irq = DMTE0_IRQ + chan; | 37 | irq = DMTE0_IRQ + chan; |
62 | } else { | 38 | } else { |
39 | #ifdef DMTE4_IRQ | ||
63 | irq = DMTE4_IRQ + chan - 4; | 40 | irq = DMTE4_IRQ + chan - 4; |
41 | #endif | ||
64 | } | 42 | } |
65 | 43 | ||
66 | return irq; | 44 | return irq; |
@@ -78,9 +56,7 @@ static inline unsigned int calc_xmit_shift(struct dma_channel *chan) | |||
78 | { | 56 | { |
79 | u32 chcr = ctrl_inl(CHCR[chan->chan]); | 57 | u32 chcr = ctrl_inl(CHCR[chan->chan]); |
80 | 58 | ||
81 | chcr >>= 4; | 59 | return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT]; |
82 | |||
83 | return ts_shift[chcr & 0x0007]; | ||
84 | } | 60 | } |
85 | 61 | ||
86 | /* | 62 | /* |
@@ -109,8 +85,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id, struct pt_regs *regs) | |||
109 | 85 | ||
110 | static int sh_dmac_request_dma(struct dma_channel *chan) | 86 | static int sh_dmac_request_dma(struct dma_channel *chan) |
111 | { | 87 | { |
88 | char name[32]; | ||
89 | |||
90 | snprintf(name, sizeof(name), "DMAC Transfer End (Channel %d)", | ||
91 | chan->chan); | ||
92 | |||
112 | return request_irq(get_dmte_irq(chan->chan), dma_tei, | 93 | return request_irq(get_dmte_irq(chan->chan), dma_tei, |
113 | SA_INTERRUPT, "DMAC Transfer End", chan); | 94 | SA_INTERRUPT, name, chan); |
114 | } | 95 | } |
115 | 96 | ||
116 | static void sh_dmac_free_dma(struct dma_channel *chan) | 97 | static void sh_dmac_free_dma(struct dma_channel *chan) |
@@ -118,10 +99,18 @@ static void sh_dmac_free_dma(struct dma_channel *chan) | |||
118 | free_irq(get_dmte_irq(chan->chan), chan); | 99 | free_irq(get_dmte_irq(chan->chan), chan); |
119 | } | 100 | } |
120 | 101 | ||
121 | static void sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr) | 102 | static void |
103 | sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr) | ||
122 | { | 104 | { |
123 | if (!chcr) | 105 | if (!chcr) |
124 | chcr = RS_DUAL; | 106 | chcr = RS_DUAL | CHCR_IE; |
107 | |||
108 | if (chcr & CHCR_IE) { | ||
109 | chcr &= ~CHCR_IE; | ||
110 | chan->flags |= DMA_TEI_CAPABLE; | ||
111 | } else { | ||
112 | chan->flags &= ~DMA_TEI_CAPABLE; | ||
113 | } | ||
125 | 114 | ||
126 | ctrl_outl(chcr, CHCR[chan->chan]); | 115 | ctrl_outl(chcr, CHCR[chan->chan]); |
127 | 116 | ||
@@ -130,22 +119,32 @@ static void sh_dmac_configure_channel(struct dma_channel *chan, unsigned long ch | |||
130 | 119 | ||
131 | static void sh_dmac_enable_dma(struct dma_channel *chan) | 120 | static void sh_dmac_enable_dma(struct dma_channel *chan) |
132 | { | 121 | { |
133 | int irq = get_dmte_irq(chan->chan); | 122 | int irq; |
134 | u32 chcr; | 123 | u32 chcr; |
135 | 124 | ||
136 | chcr = ctrl_inl(CHCR[chan->chan]); | 125 | chcr = ctrl_inl(CHCR[chan->chan]); |
137 | chcr |= CHCR_DE | CHCR_IE; | 126 | chcr |= CHCR_DE; |
127 | |||
128 | if (chan->flags & DMA_TEI_CAPABLE) | ||
129 | chcr |= CHCR_IE; | ||
130 | |||
138 | ctrl_outl(chcr, CHCR[chan->chan]); | 131 | ctrl_outl(chcr, CHCR[chan->chan]); |
139 | 132 | ||
140 | enable_irq(irq); | 133 | if (chan->flags & DMA_TEI_CAPABLE) { |
134 | irq = get_dmte_irq(chan->chan); | ||
135 | enable_irq(irq); | ||
136 | } | ||
141 | } | 137 | } |
142 | 138 | ||
143 | static void sh_dmac_disable_dma(struct dma_channel *chan) | 139 | static void sh_dmac_disable_dma(struct dma_channel *chan) |
144 | { | 140 | { |
145 | int irq = get_dmte_irq(chan->chan); | 141 | int irq; |
146 | u32 chcr; | 142 | u32 chcr; |
147 | 143 | ||
148 | disable_irq(irq); | 144 | if (chan->flags & DMA_TEI_CAPABLE) { |
145 | irq = get_dmte_irq(chan->chan); | ||
146 | disable_irq(irq); | ||
147 | } | ||
149 | 148 | ||
150 | chcr = ctrl_inl(CHCR[chan->chan]); | 149 | chcr = ctrl_inl(CHCR[chan->chan]); |
151 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); | 150 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); |
@@ -158,7 +157,7 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan) | |||
158 | * If we haven't pre-configured the channel with special flags, use | 157 | * If we haven't pre-configured the channel with special flags, use |
159 | * the defaults. | 158 | * the defaults. |
160 | */ | 159 | */ |
161 | if (!(chan->flags & DMA_CONFIGURED)) | 160 | if (unlikely(!(chan->flags & DMA_CONFIGURED))) |
162 | sh_dmac_configure_channel(chan, 0); | 161 | sh_dmac_configure_channel(chan, 0); |
163 | 162 | ||
164 | sh_dmac_disable_dma(chan); | 163 | sh_dmac_disable_dma(chan); |
@@ -178,9 +177,11 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan) | |||
178 | * cascading to the PVR2 DMAC. In this case, we still need to write | 177 | * cascading to the PVR2 DMAC. In this case, we still need to write |
179 | * SAR and DAR, regardless of value, in order for cascading to work. | 178 | * SAR and DAR, regardless of value, in order for cascading to work. |
180 | */ | 179 | */ |
181 | if (chan->sar || (mach_is_dreamcast() && chan->chan == 2)) | 180 | if (chan->sar || (mach_is_dreamcast() && |
181 | chan->chan == PVR2_CASCADE_CHAN)) | ||
182 | ctrl_outl(chan->sar, SAR[chan->chan]); | 182 | ctrl_outl(chan->sar, SAR[chan->chan]); |
183 | if (chan->dar || (mach_is_dreamcast() && chan->chan == 2)) | 183 | if (chan->dar || (mach_is_dreamcast() && |
184 | chan->chan == PVR2_CASCADE_CHAN)) | ||
184 | ctrl_outl(chan->dar, DAR[chan->chan]); | 185 | ctrl_outl(chan->dar, DAR[chan->chan]); |
185 | 186 | ||
186 | ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]); | 187 | ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]); |
@@ -198,17 +199,38 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan) | |||
198 | return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan); | 199 | return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan); |
199 | } | 200 | } |
200 | 201 | ||
201 | #if defined(CONFIG_CPU_SH4) | 202 | #ifdef CONFIG_CPU_SUBTYPE_SH7780 |
202 | static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs) | 203 | #define dmaor_read_reg() ctrl_inw(DMAOR) |
204 | #define dmaor_write_reg(data) ctrl_outw(data, DMAOR) | ||
205 | #else | ||
206 | #define dmaor_read_reg() ctrl_inl(DMAOR) | ||
207 | #define dmaor_write_reg(data) ctrl_outl(data, DMAOR) | ||
208 | #endif | ||
209 | |||
210 | static inline int dmaor_reset(void) | ||
203 | { | 211 | { |
204 | unsigned long dmaor = ctrl_inl(DMAOR); | 212 | unsigned long dmaor = dmaor_read_reg(); |
213 | |||
214 | /* Try to clear the error flags first, incase they are set */ | ||
215 | dmaor &= ~(DMAOR_NMIF | DMAOR_AE); | ||
216 | dmaor_write_reg(dmaor); | ||
205 | 217 | ||
206 | printk("DMAE: DMAOR=%lx\n", dmaor); | 218 | dmaor |= DMAOR_INIT; |
219 | dmaor_write_reg(dmaor); | ||
207 | 220 | ||
208 | ctrl_outl(ctrl_inl(DMAOR)&~DMAOR_NMIF, DMAOR); | 221 | /* See if we got an error again */ |
209 | ctrl_outl(ctrl_inl(DMAOR)&~DMAOR_AE, DMAOR); | 222 | if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) { |
210 | ctrl_outl(ctrl_inl(DMAOR)|DMAOR_DME, DMAOR); | 223 | printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n"); |
224 | return -EINVAL; | ||
225 | } | ||
211 | 226 | ||
227 | return 0; | ||
228 | } | ||
229 | |||
230 | #if defined(CONFIG_CPU_SH4) | ||
231 | static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs) | ||
232 | { | ||
233 | dmaor_reset(); | ||
212 | disable_irq(irq); | 234 | disable_irq(irq); |
213 | 235 | ||
214 | return IRQ_HANDLED; | 236 | return IRQ_HANDLED; |
@@ -224,8 +246,8 @@ static struct dma_ops sh_dmac_ops = { | |||
224 | }; | 246 | }; |
225 | 247 | ||
226 | static struct dma_info sh_dmac_info = { | 248 | static struct dma_info sh_dmac_info = { |
227 | .name = "SuperH DMAC", | 249 | .name = "sh_dmac", |
228 | .nr_channels = 4, | 250 | .nr_channels = CONFIG_NR_ONCHIP_DMA_CHANNELS, |
229 | .ops = &sh_dmac_ops, | 251 | .ops = &sh_dmac_ops, |
230 | .flags = DMAC_CHANNELS_TEI_CAPABLE, | 252 | .flags = DMAC_CHANNELS_TEI_CAPABLE, |
231 | }; | 253 | }; |
@@ -248,7 +270,13 @@ static int __init sh_dmac_init(void) | |||
248 | make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | 270 | make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); |
249 | } | 271 | } |
250 | 272 | ||
251 | ctrl_outl(0x8000 | DMAOR_DME, DMAOR); | 273 | /* |
274 | * Initialize DMAOR, and clean up any error flags that may have | ||
275 | * been set. | ||
276 | */ | ||
277 | i = dmaor_reset(); | ||
278 | if (i < 0) | ||
279 | return i; | ||
252 | 280 | ||
253 | return register_dmac(info); | 281 | return register_dmac(info); |
254 | } | 282 | } |
@@ -258,10 +286,12 @@ static void __exit sh_dmac_exit(void) | |||
258 | #ifdef CONFIG_CPU_SH4 | 286 | #ifdef CONFIG_CPU_SH4 |
259 | free_irq(DMAE_IRQ, 0); | 287 | free_irq(DMAE_IRQ, 0); |
260 | #endif | 288 | #endif |
289 | unregister_dmac(&sh_dmac_info); | ||
261 | } | 290 | } |
262 | 291 | ||
263 | subsys_initcall(sh_dmac_init); | 292 | subsys_initcall(sh_dmac_init); |
264 | module_exit(sh_dmac_exit); | 293 | module_exit(sh_dmac_exit); |
265 | 294 | ||
295 | MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh"); | ||
296 | MODULE_DESCRIPTION("SuperH On-Chip DMAC Support"); | ||
266 | MODULE_LICENSE("GPL"); | 297 | MODULE_LICENSE("GPL"); |
267 | |||
diff --git a/arch/sh/drivers/dma/dma-sh.h b/arch/sh/drivers/dma/dma-sh.h index dd9d547539a2..0f591fbc922d 100644 --- a/arch/sh/drivers/dma/dma-sh.h +++ b/arch/sh/drivers/dma/dma-sh.h | |||
@@ -11,6 +11,8 @@ | |||
11 | #ifndef __DMA_SH_H | 11 | #ifndef __DMA_SH_H |
12 | #define __DMA_SH_H | 12 | #define __DMA_SH_H |
13 | 13 | ||
14 | #include <asm/cpu/dma.h> | ||
15 | |||
14 | /* Definitions for the SuperH DMAC */ | 16 | /* Definitions for the SuperH DMAC */ |
15 | #define REQ_L 0x00000000 | 17 | #define REQ_L 0x00000000 |
16 | #define REQ_E 0x00080000 | 18 | #define REQ_E 0x00080000 |
@@ -26,27 +28,47 @@ | |||
26 | #define SM_DEC 0x00002000 | 28 | #define SM_DEC 0x00002000 |
27 | #define RS_IN 0x00000200 | 29 | #define RS_IN 0x00000200 |
28 | #define RS_OUT 0x00000300 | 30 | #define RS_OUT 0x00000300 |
29 | #define TM_BURST 0x0000080 | ||
30 | #define TS_8 0x00000010 | ||
31 | #define TS_16 0x00000020 | ||
32 | #define TS_32 0x00000030 | ||
33 | #define TS_64 0x00000000 | ||
34 | #define TS_BLK 0x00000040 | 31 | #define TS_BLK 0x00000040 |
35 | #define CHCR_DE 0x00000001 | 32 | #define CHCR_DE 0x00000001 |
36 | #define CHCR_TE 0x00000002 | 33 | #define CHCR_TE 0x00000002 |
37 | #define CHCR_IE 0x00000004 | 34 | #define CHCR_IE 0x00000004 |
38 | 35 | ||
39 | /* Define the default configuration for dual address memory-memory transfer. | 36 | /* DMAOR definitions */ |
40 | * The 0x400 value represents auto-request, external->external. | ||
41 | */ | ||
42 | #define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32) | ||
43 | |||
44 | #define DMAOR_COD 0x00000008 | ||
45 | #define DMAOR_AE 0x00000004 | 37 | #define DMAOR_AE 0x00000004 |
46 | #define DMAOR_NMIF 0x00000002 | 38 | #define DMAOR_NMIF 0x00000002 |
47 | #define DMAOR_DME 0x00000001 | 39 | #define DMAOR_DME 0x00000001 |
48 | 40 | ||
41 | /* | ||
42 | * Define the default configuration for dual address memory-memory transfer. | ||
43 | * The 0x400 value represents auto-request, external->external. | ||
44 | */ | ||
45 | #define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32) | ||
46 | |||
49 | #define MAX_DMAC_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) | 47 | #define MAX_DMAC_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) |
50 | 48 | ||
49 | /* | ||
50 | * Subtypes that have fewer channels than this simply need to change | ||
51 | * CONFIG_NR_ONCHIP_DMA_CHANNELS. Likewise, subtypes with a larger number | ||
52 | * of channels should expand on this. | ||
53 | * | ||
54 | * For most subtypes we can easily figure these values out with some | ||
55 | * basic calculation, unfortunately on other subtypes these are more | ||
56 | * scattered, so we just leave it unrolled for simplicity. | ||
57 | */ | ||
58 | #define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ | ||
59 | SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30, \ | ||
60 | SH_DMAC_BASE + 0x50, SH_DMAC_BASE + 0x60}) | ||
61 | #define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ | ||
62 | SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34, \ | ||
63 | SH_DMAC_BASE + 0x54, SH_DMAC_BASE + 0x64}) | ||
64 | #define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ | ||
65 | SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38, \ | ||
66 | SH_DMAC_BASE + 0x58, SH_DMAC_BASE + 0x68}) | ||
67 | #define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \ | ||
68 | SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c, \ | ||
69 | SH_DMAC_BASE + 0x5c, SH_DMAC_BASE + 0x6c}) | ||
70 | |||
71 | #define DMAOR (SH_DMAC_BASE + 0x40) | ||
72 | |||
51 | #endif /* __DMA_SH_H */ | 73 | #endif /* __DMA_SH_H */ |
52 | 74 | ||
diff --git a/arch/sh/drivers/dma/dma-sysfs.c b/arch/sh/drivers/dma/dma-sysfs.c index 6e3b58bd8795..70a5d82eb2f8 100644 --- a/arch/sh/drivers/dma/dma-sysfs.c +++ b/arch/sh/drivers/dma/dma-sysfs.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * sysfs interface for SH DMA API | 4 | * sysfs interface for SH DMA API |
5 | * | 5 | * |
6 | * Copyright (C) 2004 Paul Mundt | 6 | * Copyright (C) 2004, 2005 Paul Mundt |
7 | * | 7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | 8 | * This file is subject to the terms and conditions of the GNU General Public |
9 | * License. See the file "COPYING" in the main directory of this archive | 9 | * License. See the file "COPYING" in the main directory of this archive |
@@ -12,7 +12,9 @@ | |||
12 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <linux/sysdev.h> | 14 | #include <linux/sysdev.h> |
15 | #include <linux/platform_device.h> | ||
15 | #include <linux/module.h> | 16 | #include <linux/module.h> |
17 | #include <linux/err.h> | ||
16 | #include <linux/string.h> | 18 | #include <linux/string.h> |
17 | #include <asm/dma.h> | 19 | #include <asm/dma.h> |
18 | 20 | ||
@@ -77,7 +79,7 @@ static ssize_t dma_store_config(struct sys_device *dev, | |||
77 | unsigned long config; | 79 | unsigned long config; |
78 | 80 | ||
79 | config = simple_strtoul(buf, NULL, 0); | 81 | config = simple_strtoul(buf, NULL, 0); |
80 | dma_configure_channel(channel->chan, config); | 82 | dma_configure_channel(channel->vchan, config); |
81 | 83 | ||
82 | return count; | 84 | return count; |
83 | } | 85 | } |
@@ -111,12 +113,13 @@ static SYSDEV_ATTR(field, S_IRUGO, dma_show_##field, NULL); | |||
111 | dma_ro_attr(count, "0x%08x\n"); | 113 | dma_ro_attr(count, "0x%08x\n"); |
112 | dma_ro_attr(flags, "0x%08lx\n"); | 114 | dma_ro_attr(flags, "0x%08lx\n"); |
113 | 115 | ||
114 | int __init dma_create_sysfs_files(struct dma_channel *chan) | 116 | int dma_create_sysfs_files(struct dma_channel *chan, struct dma_info *info) |
115 | { | 117 | { |
116 | struct sys_device *dev = &chan->dev; | 118 | struct sys_device *dev = &chan->dev; |
119 | char name[16]; | ||
117 | int ret; | 120 | int ret; |
118 | 121 | ||
119 | dev->id = chan->chan; | 122 | dev->id = chan->vchan; |
120 | dev->cls = &dma_sysclass; | 123 | dev->cls = &dma_sysclass; |
121 | 124 | ||
122 | ret = sysdev_register(dev); | 125 | ret = sysdev_register(dev); |
@@ -129,6 +132,24 @@ int __init dma_create_sysfs_files(struct dma_channel *chan) | |||
129 | sysdev_create_file(dev, &attr_flags); | 132 | sysdev_create_file(dev, &attr_flags); |
130 | sysdev_create_file(dev, &attr_config); | 133 | sysdev_create_file(dev, &attr_config); |
131 | 134 | ||
132 | return 0; | 135 | snprintf(name, sizeof(name), "dma%d", chan->chan); |
136 | return sysfs_create_link(&info->pdev->dev.kobj, &dev->kobj, name); | ||
137 | } | ||
138 | |||
139 | void dma_remove_sysfs_files(struct dma_channel *chan, struct dma_info *info) | ||
140 | { | ||
141 | struct sys_device *dev = &chan->dev; | ||
142 | char name[16]; | ||
143 | |||
144 | sysdev_remove_file(dev, &attr_dev_id); | ||
145 | sysdev_remove_file(dev, &attr_count); | ||
146 | sysdev_remove_file(dev, &attr_mode); | ||
147 | sysdev_remove_file(dev, &attr_flags); | ||
148 | sysdev_remove_file(dev, &attr_config); | ||
149 | |||
150 | snprintf(name, sizeof(name), "dma%d", chan->chan); | ||
151 | sysfs_remove_link(&info->pdev->dev.kobj, name); | ||
152 | |||
153 | sysdev_unregister(dev); | ||
133 | } | 154 | } |
134 | 155 | ||
diff --git a/arch/sh/kernel/cpu/bus.c b/arch/sh/kernel/cpu/bus.c index 3278d234bb1b..fc6c4bd40c65 100644 --- a/arch/sh/kernel/cpu/bus.c +++ b/arch/sh/kernel/cpu/bus.c | |||
@@ -109,6 +109,8 @@ int sh_device_register(struct sh_dev *dev) | |||
109 | /* This is needed for USB OHCI to work */ | 109 | /* This is needed for USB OHCI to work */ |
110 | if (dev->dma_mask) | 110 | if (dev->dma_mask) |
111 | dev->dev.dma_mask = dev->dma_mask; | 111 | dev->dev.dma_mask = dev->dma_mask; |
112 | if (dev->coherent_dma_mask) | ||
113 | dev->dev.coherent_dma_mask = dev->coherent_dma_mask; | ||
112 | 114 | ||
113 | snprintf(dev->dev.bus_id, BUS_ID_SIZE, "%s%u", | 115 | snprintf(dev->dev.bus_id, BUS_ID_SIZE, "%s%u", |
114 | dev->name, dev->dev_id); | 116 | dev->name, dev->dev_id); |