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authorMagnus Damm <damm@opensource.se>2010-05-11 01:00:47 -0400
committerPaul Mundt <lethal@linux-sh.org>2010-05-13 04:33:17 -0400
commitc77a9c3edee079fe0411d98cfb9d872bc336ee32 (patch)
treeb368c77d6b391c37ff1674baaf5334ab3092ec1f /arch/sh
parentd8ef3ccc1c99ae51128b28aaed6e8afc43af71ff (diff)
sh: get rid of mstp32 clock name and id
Remove the name and the id from SH_CLK_MSTP32(). Now when lookups are handled by clkdev they are not needed anymore. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/include/asm/clock.h15
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c93
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c82
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c42
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c58
5 files changed, 143 insertions, 147 deletions
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 405a12c09960..c52882c1a468 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -116,15 +116,12 @@ int clk_rate_table_find(struct clk *clk,
116 struct cpufreq_frequency_table *freq_table, 116 struct cpufreq_frequency_table *freq_table,
117 unsigned long rate); 117 unsigned long rate);
118 118
119#define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \ 119#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
120 _enable_bit, _flags) \ 120{ \
121{ \ 121 .parent = _parent, \
122 .name = _name, \ 122 .enable_reg = (void __iomem *)_enable_reg, \
123 .id = _id, \ 123 .enable_bit = _enable_bit, \
124 .parent = _parent, \ 124 .flags = _flags, \
125 .enable_reg = (void __iomem *)_enable_reg, \
126 .enable_bit = _enable_bit, \
127 .flags = _flags, \
128} 125}
129 126
130int sh_clk_mstp32_register(struct clk *clks, int nr); 127int sh_clk_mstp32_register(struct clk *clks, int nr);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index f661d4633573..0aabb5d31356 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -142,8 +142,8 @@ struct clk div6_clks[DIV6_NR] = {
142 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 142 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
143}; 143};
144 144
145#define MSTP(_str, _parent, _reg, _bit, _flags) \ 145#define MSTP(_parent, _reg, _bit, _flags) \
146 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 146 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
147 147
148enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026, 148enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
149 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016, 149 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
@@ -156,50 +156,50 @@ enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
156 MSTP_NR }; 156 MSTP_NR };
157 157
158static struct clk mstp_clks[MSTP_NR] = { 158static struct clk mstp_clks[MSTP_NR] = {
159 [MSTP031] = MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 159 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
160 [MSTP030] = MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 160 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
161 [MSTP029] = MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 161 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
162 [MSTP028] = MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 162 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
163 [MSTP026] = MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 163 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
164 [MSTP023] = MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 164 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
165 [MSTP022] = MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 165 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
166 [MSTP021] = MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 166 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
167 [MSTP020] = MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 167 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
168 [MSTP019] = MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 168 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
169 [MSTP017] = MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 169 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
170 [MSTP015] = MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 170 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
171 [MSTP014] = MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0), 171 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
172 [MSTP013] = MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 172 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
173 [MSTP011] = MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 173 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
174 [MSTP010] = MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 174 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
175 [MSTP007] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0), 175 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
176 [MSTP006] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0), 176 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
177 [MSTP005] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 177 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
178 [MSTP004] = SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0), 178 [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
179 [MSTP003] = MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), 179 [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
180 [MSTP002] = MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 180 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
181 [MSTP001] = MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 181 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
182 182
183 [MSTP109] = MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 183 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
184 [MSTP108] = MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), 184 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
185 185
186 [MSTP225] = MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), 186 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
187 [MSTP224] = MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 187 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
188 [MSTP218] = MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 188 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
189 [MSTP217] = MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 189 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
190 [MSTP216] = MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), 190 [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
191 [MSTP214] = MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), 191 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
192 [MSTP213] = MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), 192 [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
193 [MSTP212] = MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), 193 [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
194 [MSTP211] = MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 194 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
195 [MSTP208] = MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), 195 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
196 [MSTP206] = MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 196 [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
197 [MSTP205] = MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 197 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
198 [MSTP204] = MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 198 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
199 [MSTP203] = MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 199 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
200 [MSTP202] = MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 200 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
201 [MSTP201] = MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 201 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
202 [MSTP200] = MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 202 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
203}; 203};
204 204
205#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 205#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
@@ -216,7 +216,6 @@ static struct clk_lookup lookups[] = {
216 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]), 216 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
217 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]), 217 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
218 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]), 218 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
219
220 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]), 219 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
221 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]), 220 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
222 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]), 221 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 5649bfcb9f74..a3ef183656fa 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -145,8 +145,8 @@ struct clk div6_clks[DIV6_NR] = {
145 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 145 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
146}; 146};
147 147
148#define MSTP(_str, _parent, _reg, _bit, _flags) \ 148#define MSTP(_parent, _reg, _bit, _flags) \
149 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 149 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
150 150
151enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026, 151enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
152 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016, 152 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
@@ -159,45 +159,45 @@ enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
159 159
160static struct clk mstp_clks[MSTP_NR] = { 160static struct clk mstp_clks[MSTP_NR] = {
161 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ 161 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
162 [MSTP031] = MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 162 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
163 [MSTP030] = MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 163 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
164 [MSTP029] = MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 164 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
165 [MSTP028] = MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 165 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
166 [MSTP026] = MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 166 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
167 [MSTP023] = MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 167 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
168 [MSTP022] = MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 168 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
169 [MSTP021] = MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 169 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
170 [MSTP020] = MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 170 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
171 [MSTP019] = MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 171 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
172 [MSTP017] = MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 172 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
173 [MSTP015] = MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 173 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
174 [MSTP014] = MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0), 174 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
175 [MSTP013] = MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 175 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
176 [MSTP011] = MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 176 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
177 [MSTP010] = MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 177 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
178 [MSTP007] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0), 178 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
179 [MSTP006] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0), 179 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
180 [MSTP005] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 180 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
181 [MSTP002] = MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 181 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
182 [MSTP001] = MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 182 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
183 183
184 [MSTP109] = MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 184 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
185 185
186 [MSTP227] = MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0), 186 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
187 [MSTP226] = MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0), 187 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
188 [MSTP224] = MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 188 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
189 [MSTP223] = MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0), 189 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
190 [MSTP222] = MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0), 190 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
191 [MSTP218] = MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 191 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
192 [MSTP217] = MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 192 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
193 [MSTP211] = MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 193 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
194 [MSTP207] = MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), 194 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
195 [MSTP205] = MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 195 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
196 [MSTP204] = MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 196 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
197 [MSTP203] = MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 197 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
198 [MSTP202] = MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 198 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
199 [MSTP201] = MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 199 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
200 [MSTP200] = MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 200 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
201}; 201};
202 202
203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 24d7208ff705..4625b72ba50c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -95,29 +95,29 @@ enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
95 95
96static struct clk mstp_clks[MSTP_NR] = { 96static struct clk mstp_clks[MSTP_NR] = {
97 /* MSTPCR0 */ 97 /* MSTPCR0 */
98 [MSTP029] = SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 98 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
99 [MSTP028] = SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 99 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
100 [MSTP027] = SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 100 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
101 [MSTP026] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 101 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
102 [MSTP025] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 102 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
103 [MSTP024] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 103 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
104 [MSTP021] = SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 104 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
105 [MSTP020] = SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 105 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
106 [MSTP017] = SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 106 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
107 [MSTP016] = SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 107 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
108 [MSTP013] = SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), 108 [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
109 [MSTP012] = SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), 109 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
110 [MSTP009] = SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 110 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
111 [MSTP008] = SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 111 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
112 [MSTP003] = SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), 112 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
113 [MSTP002] = SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 113 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
114 114
115 /* MSTPCR1 */ 115 /* MSTPCR1 */
116 [MSTP119] = SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), 116 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
117 [MSTP117] = SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), 117 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
118 [MSTP105] = SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 118 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
119 [MSTP104] = SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 119 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
120 [MSTP100] = SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), 120 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
121}; 121};
122 122
123#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 123#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index d4f5f46883af..653d96615b77 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -97,37 +97,37 @@ enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
97 97
98static struct clk mstp_clks[MSTP_NR] = { 98static struct clk mstp_clks[MSTP_NR] = {
99 /* MSTPCR0 */ 99 /* MSTPCR0 */
100 [MSTP029] = SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 100 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
101 [MSTP028] = SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 101 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
102 [MSTP027] = SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 102 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
103 [MSTP026] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 103 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
104 [MSTP025] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 104 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
105 [MSTP024] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 105 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
106 [MSTP023] = SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), 106 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
107 [MSTP022] = SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), 107 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
108 [MSTP021] = SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 108 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
109 [MSTP020] = SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 109 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
110 [MSTP017] = SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 110 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
111 [MSTP016] = SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 111 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
112 [MSTP015] = SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0), 112 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
113 [MSTP014] = SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0), 113 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
114 [MSTP011] = SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0), 114 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
115 [MSTP010] = SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0), 115 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
116 [MSTP009] = SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 116 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
117 [MSTP008] = SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 117 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
118 [MSTP005] = SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 118 [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
119 [MSTP004] = SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0), 119 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
120 [MSTP002] = SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 120 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
121 121
122 /* MSTPCR1 */ 122 /* MSTPCR1 */
123 [MSTP112] = SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0), 123 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
124 [MSTP110] = SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0), 124 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
125 [MSTP109] = SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0), 125 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
126 [MSTP108] = SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0), 126 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
127 [MSTP105] = SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 127 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
128 [MSTP104] = SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 128 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
129 [MSTP103] = SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0), 129 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
130 [MSTP102] = SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0), 130 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
131}; 131};
132 132
133#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 133#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 18:58:47 -0500